[clang] [llvm] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (PR #124706)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 24 01:05:15 PST 2025
https://github.com/hchandel updated https://github.com/llvm/llvm-project/pull/124706
>From 81d1b6240cfaedb521d4f0efd54744114577f455 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <hchandel at qti.qualcomm.com>
Date: Fri, 24 Jan 2025 16:43:12 +0530
Subject: [PATCH 1/6] [RISCV] Add Qualcomm uC Xqcilia (Large Immediate
Arithmetic) extension This extension adds eight 48 bit large arithmetic
instructions.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Change-Id: Id7712ee41128ba11a3752cb4c2450a9c7be8e7d7
---
.../Driver/print-supported-extensions-riscv.c | 1 +
llvm/docs/RISCVUsage.rst | 3 +
llvm/docs/ReleaseNotes.md | 2 +
.../RISCV/Disassembler/RISCVDisassembler.cpp | 4 +-
llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 33 ++++++
llvm/lib/TargetParser/RISCVISAInfo.cpp | 3 +-
llvm/test/CodeGen/RISCV/attributes.ll | 2 +
llvm/test/MC/RISCV/xqcilia-invalid.s | 109 ++++++++++++++++++
llvm/test/MC/RISCV/xqcilia-valid.s | 82 +++++++++++++
.../TargetParser/RISCVISAInfoTest.cpp | 3 +-
11 files changed, 247 insertions(+), 3 deletions(-)
create mode 100644 llvm/test/MC/RISCV/xqcilia-invalid.s
create mode 100644 llvm/test/MC/RISCV/xqcilia-valid.s
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index ae3a1c29df397..7dbece2a148c7 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -197,6 +197,7 @@
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
+// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index c83fd1db0ba9b..dc367131f13e7 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -450,6 +450,9 @@ The current vendor extensions supported are:
``experimental-Xqciint``
LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+``experimental-Xqcilia``
+ LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
+
``experimental-Xqcilo``
LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 05d902641d093..d8a222920ee29 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -296,6 +296,8 @@ Changes to the RISC-V Backend
extension.
* Adds experimental assembler support for the Qualcomm uC 'Xqcilo` (Large Offset Load Store)
extension.
+* Adds experimental assembler support for the Qualcomm uC 'Xqcilia` (Large Immediate Arithmetic)
+ extension.
* Added ``Sdext`` and ``Sdtrig`` extensions.
Changes to the WebAssembly Backend
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index a0b87f7c7ff25..a7db6a13a3d63 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -766,7 +766,9 @@ DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
TRY_TO_DECODE_FEATURE(
RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
"Qualcomm uC Large Offset Load Store custom 48bit opcode table");
-
+ TRY_TO_DECODE_FEATURE(
+ RISCV::FeatureVendorXqcilia, DecoderTableXqcilia48,
+ "Qualcomm uC Large Immediate Arithmetic custom 48bit opcode table");
return MCDisassembler::Fail;
}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 4119dd77804f1..542d4935a90a4 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1310,6 +1310,14 @@ def HasVendorXqciint
AssemblerPredicate<(all_of FeatureVendorXqciint),
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
+def FeatureVendorXqcilia
+ : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
+ [FeatureStdExtZca]>;
+def HasVendorXqcilia
+ : Predicate<"Subtarget->hasVendorXqcilia()">,
+ AssemblerPredicate<(all_of FeatureVendorXqcilia),
+ "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
+
def FeatureVendorXqcilo
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
[FeatureStdExtZca]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index f746cce8c9a0f..1b84cf6a35b16 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -245,6 +245,25 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
opcodestr, "$rs2, ${imm}(${rs1})">;
+class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
+ : RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, imm32:$imm),
+ opcodestr, "$rd, $imm", [], InstFormatOther> {
+ bits<5> rd;
+ bits<32> imm;
+
+ let Constraints = "$rd = $rd_wb";
+ let Inst{47-16} = imm{31-0};
+ let Inst{15} = funct1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = 0b0011111;
+}
+
+class QCIRVInstEI<bits<3> funct3, bits<2> funct2, string opcodestr>
+ : QCIRVInstEIBase<funct3, funct2, (outs GPRNoX0:$rd),
+ (ins GPRNoX0:$rs1, simm26:$imm), opcodestr,
+ "$rd, $rs1, $imm">;
+
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
@@ -435,6 +454,20 @@ let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
+let Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia" in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ def QC_E_XORAI : QCIRVInstEAI<0b001, 0b0, "qc.e.xorai">;
+ def QC_E_ORAI : QCIRVInstEAI<0b001, 0b1, "qc.e.orai" >;
+ def QC_E_ADDAI : QCIRVInstEAI<0b010, 0b0, "qc.e.addai">;
+ def QC_E_ANDAI : QCIRVInstEAI<0b010, 0b1, "qc.e.andai">;
+
+ def QC_E_XORI : QCIRVInstEI<0b011, 0b00, "qc.e.xori">;
+ def QC_E_ORI : QCIRVInstEI<0b011, 0b01, "qc.e.ori" >;
+ def QC_E_ADDI : QCIRVInstEI<0b011, 0b10, "qc.e.addi">;
+ def QC_E_ANDI : QCIRVInstEI<0b011, 0b11, "qc.e.andi">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // Predicates = [HasVendorXqcilia, IsRV32], DecoderNamespace = "Xqcilia"
+
//===----------------------------------------------------------------------===//
// Aliases
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index c78d60fd86b3f..3ded9ce64ad59 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -743,7 +743,8 @@ Error RISCVISAInfo::checkDependency() {
bool HasZcmt = Exts.count("zcmt") != 0;
static constexpr StringLiteral XqciExts[] = {
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
- {"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
+ {"xqcicsr"}, {"xqciint"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"},
+ {"xqcisls"}};
if (HasI && HasE)
return getIncompatibleError("i", "e");
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index caed0bdfb0498..b4b08939a7468 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -88,6 +88,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s
@@ -404,6 +405,7 @@
; RV32XQCICS: .attribute 5, "rv32i2p1_xqcics0p2"
; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
; RV32XQCIINT: .attribute 5, "rv32i2p1_zca1p0_xqciint0p2"
+; RV32XQCILIA: .attribute 5, "rv32i2p1_zca1p0_xqcilia0p2"
; RV32XQCILO: .attribute 5, "rv32i2p1_zca1p0_xqcilo0p2"
; RV32XQCILSM: .attribute 5, "rv32i2p1_xqcilsm0p2"
; RV32XQCISLS: .attribute 5, "rv32i2p1_xqcisls0p2"
diff --git a/llvm/test/MC/RISCV/xqcilia-invalid.s b/llvm/test/MC/RISCV/xqcilia-invalid.s
new file mode 100644
index 0000000000000..e39efd9de7335
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilia-invalid.s
@@ -0,0 +1,109 @@
+# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s
+# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilia < %s 2>&1 \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.addai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.addai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.addai x9, 20485546494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.addai x9, 33554432
+
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.addi x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.addi x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.addi x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.addi x10, x9, 554432
+
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.andai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.andai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.andai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.andai x9, 33554432
+
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.andi x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.andi x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.andi x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.andi x10, x9, 554432
+
+
+# CHECK: :[[@LINE+1]]:11: error: invalid operand for instruction
+qc.e.orai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.orai x9
+
+# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.orai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.orai x9, 33554432
+
+
+# CHECK: :[[@LINE+1]]:15: error: invalid operand for instruction
+qc.e.ori x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.ori x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:19: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.ori x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.ori x10, x9, 554432
+
+
+
+# CHECK: :[[@LINE+1]]:12: error: invalid operand for instruction
+qc.e.xorai 9, 33554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.xorai x9
+
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+qc.e.xorai x9, 20494437494
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.xorai x9, 33554432
+
+
+# CHECK: :[[@LINE+1]]:16: error: invalid operand for instruction
+qc.e.xori x10, 9, 554432
+
+# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
+qc.e.xori x10, x9
+
+# CHECK-IMM: :[[@LINE+1]]:20: error: immediate must be an integer in the range [-33554432, 33554431]
+qc.e.xori x10, x9, 335544312
+
+# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+qc.e.xori x10, x9, 554432
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
new file mode 100644
index 0000000000000..49727d5d36239
--- /dev/null
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -0,0 +1,82 @@
+# Xqcilia - Qualcomm uC Large Immediate Arithmetic extension
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \
+# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
+# RUN: | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: qc.e.addai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
+qc.e.addai x9, 4294967295
+
+# CHECK-INST: qc.e.addai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
+qc.e.addai x9, -2147483648
+
+
+# CHECK-INST: qc.e.addi a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x80,0x00,0x80]
+qc.e.addi x10, x9, -33554432
+
+# CHECK-INST: qc.e.addi a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xbf,0xff,0x7f]
+qc.e.addi x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.andai s1, -1
+# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
+qc.e.andai x9, 4294967295
+
+# CHECK-INST: qc.e.andai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
+qc.e.andai x9, -2147483648
+
+
+# CHECK-INST: qc.e.andi a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0xc0,0x00,0x80]
+qc.e.andi x10, x9, -33554432
+
+# CHECK-INST: qc.e.andi a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0xff,0xff,0x7f]
+qc.e.andi x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.orai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
+qc.e.orai x9, 4294967295
+
+# CHECK-INST: qc.e.orai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
+qc.e.orai x9, -2147483648
+
+
+# CHECK-INST: qc.e.ori a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x40,0x00,0x80]
+qc.e.ori x10, x9, -33554432
+
+# CHECK-INST: qc.e.ori a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x7f,0xff,0x7f]
+qc.e.ori x10, x9, 33554431
+
+
+# CHECK-INST: qc.e.xorai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
+qc.e.xorai x9, 4294967295
+
+# CHECK-INST: qc.e.xorai s1, -2147483648
+# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
+qc.e.xorai x9, -2147483648
+
+
+# CHECK-INST: qc.e.xori a0, s1, -33554432
+# CHECK-ENC: encoding: [0x1f,0xb5,0x04,0x00,0x00,0x80]
+qc.e.xori x10, x9, -33554432
+
+# CHECK-INST: qc.e.xori a0, s1, 33554431
+# CHECK-ENC: encoding: [0x1f,0xb5,0xf4,0x3f,0xff,0x7f]
+qc.e.xori x10, x9, 33554431
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index 14a60c1857f24..81d76f5aac37e 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -657,7 +657,7 @@ TEST(ParseArchString, RejectsConflictingExtensions) {
{"rv64i_xqcisls0p2", "rv64i_xqcia0p2", "rv64i_xqciac0p2",
"rv64i_xqcicsr0p2", "rv64i_xqcilsm0p2", "rv64i_xqcicm0p2",
"rv64i_xqcics0p2", "rv64i_xqcicli0p2", "rv64i_xqciint0p2",
- "rv64i_xqcilo0p2"}) {
+ "rv64i_xqcilo0p2", "rv64i_xqcilia0p2"}) {
EXPECT_THAT(
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
::testing::EndsWith(" is only supported for 'rv32'"));
@@ -1123,6 +1123,7 @@ Experimental extensions
xqcics 0.2
xqcicsr 0.2
xqciint 0.2
+ xqcilia 0.2
xqcilo 0.2
xqcilsm 0.2
xqcisls 0.2
>From b9501ff7b70d87715fd058474b2e079e12037650 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Tue, 28 Jan 2025 11:53:19 +0530
Subject: [PATCH 2/6] Add support for Operand Imm32
Change-Id: I49b82a0333ab216d7b150027d973f11d4cbdf35c
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 18 ++++++++++++++++++
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 +
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 15 +++++++++++++++
3 files changed, 34 insertions(+)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 227a6361730da..19afda3219e77 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1046,6 +1046,20 @@ struct RISCVOperand final : public MCParsedAsmOperand {
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
}
+ bool isImm32() const {
+ int64_t Imm;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ if (!isImm())
+ return false;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ bool IsValid;
+ if (!IsConstantImm)
+ IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
+ else
+ IsValid = isInt<32>(Imm) || isUInt<32>(Imm);
+ return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -1689,6 +1703,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSImm26:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
(1 << 25) - 1);
+ case Match_InvalidImm32:
+ return generateImmOutOfRangeError(Operands, ErrorInfo,
+ std::numeric_limits<int32_t>::min(),
+ std::numeric_limits<uint32_t>::max());
case Match_InvalidRlist: {
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index e9abc90d69a13..6ea038ce4110e 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -333,6 +333,7 @@ enum OperandType : unsigned {
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM26,
+ OPERAND_IMM32,
OPERAND_CLUI_IMM,
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 1b84cf6a35b16..f014695a18bdd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -34,6 +34,21 @@ def uimm11 : RISCVUImmLeafOp<11>;
def simm26 : RISCVSImmLeafOp<26>;
+// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
+// sign-/zero-extension. This is represented internally as a signed 32-bit value.
+def imm32 : RISCVOp<XLenVT> {
+ let ParserMatchClass = ImmAsmOperand<"", 32, "">;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeSImmOperand<32>";
+ let OperandType = "OPERAND_IMM32";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return (isInt<32>(Imm) || isUint<32>(Imm));
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
//===----------------------------------------------------------------------===//
// Instruction Formats
//===----------------------------------------------------------------------===//
>From 34f05e851cb83129e7c8c90460642d2a0f2e63a0 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Tue, 28 Jan 2025 12:16:27 +0530
Subject: [PATCH 3/6] Update RISCVISAInfo.cpp
Change-Id: Ifc27c895f1542261efd76b0a3f4f95563ad16b77
---
llvm/lib/TargetParser/RISCVISAInfo.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp
index 3ded9ce64ad59..132c47ca631b6 100644
--- a/llvm/lib/TargetParser/RISCVISAInfo.cpp
+++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp
@@ -742,9 +742,9 @@ Error RISCVISAInfo::checkDependency() {
bool HasZvl = MinVLen != 0;
bool HasZcmt = Exts.count("zcmt") != 0;
static constexpr StringLiteral XqciExts[] = {
- {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
- {"xqcicsr"}, {"xqciint"}, {"xqcilia"}, {"xqcilo"}, {"xqcilsm"},
- {"xqcisls"}};
+ {"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"},
+ {"xqcics"}, {"xqcicsr"}, {"xqciint"}, {"xqcilia"},
+ {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
if (HasI && HasE)
return getIncompatibleError("i", "e");
>From 71206e8f2f8e2c29756dd2d5a3d63631aec76979 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Fri, 21 Feb 2025 14:40:47 +0530
Subject: [PATCH 4/6] Change Imm32 to SImm32
Change-Id: I1138c145571be288f566598214ebe183e1dfb99c
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 13 ++++------
.../Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 2 +-
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 12 +++++-----
llvm/test/MC/RISCV/xqcilia-invalid.s | 8 +++----
llvm/test/MC/RISCV/xqcilia-valid.s | 24 +++++++++----------
5 files changed, 27 insertions(+), 32 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 6586038353373..a2416130e9941 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1056,18 +1056,13 @@ struct RISCVOperand final : public MCParsedAsmOperand {
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
}
- bool isImm32() const {
+ bool isSImm32() const {
int64_t Imm;
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
- bool IsValid;
- if (!IsConstantImm)
- IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK);
- else
- IsValid = isInt<32>(Imm) || isUInt<32>(Imm);
- return IsValid && VK == RISCVMCExpr::VK_RISCV_None;
+ return IsConstantImm && isInt<32>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
}
/// getStartLoc - Gets location of the first token of this operand
@@ -1679,10 +1674,10 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSImm26:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
(1 << 25) - 1);
- case Match_InvalidImm32:
+ case Match_InvalidSImm32:
return generateImmOutOfRangeError(Operands, ErrorInfo,
std::numeric_limits<int32_t>::min(),
- std::numeric_limits<uint32_t>::max());
+ std::numeric_limits<int32_t>::max());
case Match_InvalidRnumArg: {
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index d0888a8ce7785..51ad5120b7efa 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -326,7 +326,7 @@ enum OperandType : unsigned {
OPERAND_SIMM12,
OPERAND_SIMM12_LSB00000,
OPERAND_SIMM26,
- OPERAND_IMM32,
+ OPERAND_SIMM32,
OPERAND_CLUI_IMM,
OPERAND_VTYPEI10,
OPERAND_VTYPEI11,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 23f40712ad1ad..3a8039fce1f49 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -36,16 +36,16 @@ def simm26 : RISCVSImmLeafOp<26>;
// 32-bit Immediate, used by RV32 Instructions in 32-bit operations, so no
// sign-/zero-extension. This is represented internally as a signed 32-bit value.
-def imm32 : RISCVOp<XLenVT> {
- let ParserMatchClass = ImmAsmOperand<"", 32, "">;
+def simm32 : RISCVOp<XLenVT> {
+ let ParserMatchClass = SImmAsmOperand<32, "">;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<32>";
- let OperandType = "OPERAND_IMM32";
+ let OperandType = "OPERAND_SIMM32";
let MCOperandPredicate = [{
int64_t Imm;
if (MCOp.evaluateAsConstantImm(Imm))
- return (isInt<32>(Imm));
- return MCOp.isBareSymbolRef();
+ return isInt<32>(Imm);
+ return false;
}];
}
@@ -261,7 +261,7 @@ class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
opcodestr, "$rs2, ${imm}(${rs1})">;
class QCIRVInstEAI<bits<3> funct3, bits<1> funct1, string opcodestr>
- : RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, imm32:$imm),
+ : RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm32:$imm),
opcodestr, "$rd, $imm", [], InstFormatOther> {
bits<5> rd;
bits<32> imm;
diff --git a/llvm/test/MC/RISCV/xqcilia-invalid.s b/llvm/test/MC/RISCV/xqcilia-invalid.s
index 50b56bc0db41d..39fb872cff647 100644
--- a/llvm/test/MC/RISCV/xqcilia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilia-invalid.s
@@ -11,7 +11,7 @@ qc.e.addai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.addai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
qc.e.addai x9, 20485546494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -39,7 +39,7 @@ qc.e.andai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.andai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
qc.e.andai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -67,7 +67,7 @@ qc.e.orai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.orai x9
-# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
+# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 2147483647]
qc.e.orai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -96,7 +96,7 @@ qc.e.xorai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.xorai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
qc.e.xorai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
index 49727d5d36239..3f91fc9c0774c 100644
--- a/llvm/test/MC/RISCV/xqcilia-valid.s
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -10,9 +10,9 @@
# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: qc.e.addai s1, -1
-# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
-qc.e.addai x9, 4294967295
+# CHECK-INST: qc.e.addai s1, 2147483647
+# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0x7f]
+qc.e.addai x9, 2147483647
# CHECK-INST: qc.e.addai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
@@ -28,9 +28,9 @@ qc.e.addi x10, x9, -33554432
qc.e.addi x10, x9, 33554431
-# CHECK-INST: qc.e.andai s1, -1
-# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
-qc.e.andai x9, 4294967295
+# CHECK-INST: qc.e.andai s1, 2147483647
+# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0x7f]
+qc.e.andai x9, 2147483647
# CHECK-INST: qc.e.andai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
@@ -46,9 +46,9 @@ qc.e.andi x10, x9, -33554432
qc.e.andi x10, x9, 33554431
-# CHECK-INST: qc.e.orai s1, -1
-# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
-qc.e.orai x9, 4294967295
+# CHECK-INST: qc.e.orai s1, 2147483647
+# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0x7f]
+qc.e.orai x9, 2147483647
# CHECK-INST: qc.e.orai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
@@ -64,9 +64,9 @@ qc.e.ori x10, x9, -33554432
qc.e.ori x10, x9, 33554431
-# CHECK-INST: qc.e.xorai s1, -1
-# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
-qc.e.xorai x9, 4294967295
+# CHECK-INST: qc.e.xorai s1, 2147483647
+# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0x7f]
+qc.e.xorai x9, 2147483647
# CHECK-INST: qc.e.xorai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
>From 1df40d1c177175cb152ed903f5bb9fa9a1caadf0 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 24 Feb 2025 11:54:39 +0530
Subject: [PATCH 5/6] Fix SImm32
Change-Id: Id8c71e493c60e85bf5c7013f15984ffeadf1951b
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 ++--
llvm/test/MC/RISCV/xqcilia-invalid.s | 8 +++----
llvm/test/MC/RISCV/xqcilia-valid.s | 24 +++++++++----------
3 files changed, 19 insertions(+), 18 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index a2416130e9941..48d4f11f02662 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1062,7 +1062,8 @@ struct RISCVOperand final : public MCParsedAsmOperand {
if (!isImm())
return false;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
- return IsConstantImm && isInt<32>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+ return IsConstantImm && isInt<32>(fixImmediateForRV32(Imm, isRV64Imm())) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
}
/// getStartLoc - Gets location of the first token of this operand
@@ -1677,7 +1678,7 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidSImm32:
return generateImmOutOfRangeError(Operands, ErrorInfo,
std::numeric_limits<int32_t>::min(),
- std::numeric_limits<int32_t>::max());
+ std::numeric_limits<uint32_t>::max());
case Match_InvalidRnumArg: {
return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
}
diff --git a/llvm/test/MC/RISCV/xqcilia-invalid.s b/llvm/test/MC/RISCV/xqcilia-invalid.s
index 39fb872cff647..50b56bc0db41d 100644
--- a/llvm/test/MC/RISCV/xqcilia-invalid.s
+++ b/llvm/test/MC/RISCV/xqcilia-invalid.s
@@ -11,7 +11,7 @@ qc.e.addai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.addai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
qc.e.addai x9, 20485546494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -39,7 +39,7 @@ qc.e.andai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.andai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
qc.e.andai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -67,7 +67,7 @@ qc.e.orai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.orai x9
-# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 2147483647]
+# CHECK-IMM: :[[@LINE+1]]:15: error: immediate must be an integer in the range [-2147483648, 4294967295]
qc.e.orai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
@@ -96,7 +96,7 @@ qc.e.xorai 9, 33554432
# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
qc.e.xorai x9
-# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 2147483647]
+# CHECK-IMM: :[[@LINE+1]]:16: error: immediate must be an integer in the range [-2147483648, 4294967295]
qc.e.xorai x9, 20494437494
# CHECK-EXT: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s
index 3f91fc9c0774c..49727d5d36239 100644
--- a/llvm/test/MC/RISCV/xqcilia-valid.s
+++ b/llvm/test/MC/RISCV/xqcilia-valid.s
@@ -10,9 +10,9 @@
# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# CHECK-INST: qc.e.addai s1, 2147483647
-# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0x7f]
-qc.e.addai x9, 2147483647
+# CHECK-INST: qc.e.addai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x24,0xff,0xff,0xff,0xff]
+qc.e.addai x9, 4294967295
# CHECK-INST: qc.e.addai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x24,0x00,0x00,0x00,0x80]
@@ -28,9 +28,9 @@ qc.e.addi x10, x9, -33554432
qc.e.addi x10, x9, 33554431
-# CHECK-INST: qc.e.andai s1, 2147483647
-# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0x7f]
-qc.e.andai x9, 2147483647
+# CHECK-INST: qc.e.andai s1, -1
+# CHECK-ENC: encoding: [0x9f,0xa4,0xff,0xff,0xff,0xff]
+qc.e.andai x9, 4294967295
# CHECK-INST: qc.e.andai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0xa4,0x00,0x00,0x00,0x80]
@@ -46,9 +46,9 @@ qc.e.andi x10, x9, -33554432
qc.e.andi x10, x9, 33554431
-# CHECK-INST: qc.e.orai s1, 2147483647
-# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0x7f]
-qc.e.orai x9, 2147483647
+# CHECK-INST: qc.e.orai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x94,0xff,0xff,0xff,0xff]
+qc.e.orai x9, 4294967295
# CHECK-INST: qc.e.orai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x94,0x00,0x00,0x00,0x80]
@@ -64,9 +64,9 @@ qc.e.ori x10, x9, -33554432
qc.e.ori x10, x9, 33554431
-# CHECK-INST: qc.e.xorai s1, 2147483647
-# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0x7f]
-qc.e.xorai x9, 2147483647
+# CHECK-INST: qc.e.xorai s1, -1
+# CHECK-ENC: encoding: [0x9f,0x14,0xff,0xff,0xff,0xff]
+qc.e.xorai x9, 4294967295
# CHECK-INST: qc.e.xorai s1, -2147483648
# CHECK-ENC: encoding: [0x9f,0x14,0x00,0x00,0x00,0x80]
>From 0b404817017d98d77f7846fe3579897aaca9c6d7 Mon Sep 17 00:00:00 2001
From: Harsh Chandel <quic_hchandel at quicinc.com>
Date: Mon, 24 Feb 2025 14:29:51 +0530
Subject: [PATCH 6/6] Fix Indentation
Change-Id: Iede8b12c1a8a59058969d8431bb7f66ca91c770e
---
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 48d4f11f02662..650ad48e50de0 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1063,7 +1063,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
return false;
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
return IsConstantImm && isInt<32>(fixImmediateForRV32(Imm, isRV64Imm())) &&
- VK == RISCVMCExpr::VK_RISCV_None;
+ VK == RISCVMCExpr::VK_RISCV_None;
}
/// getStartLoc - Gets location of the first token of this operand
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