[llvm] [AMDGPU] Enable "amdgpu-uniform-intrinsic-combine" pass in pipeline. (PR #128687)

[Christudasan Devadasan via llvm-commits]

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@@ -1,3 +1,4 @@
+; XFAIL: *  
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cdevadas wrote:

> > **$sgpr0 = COPY %4:vgpr_32**
> > SI_RETURN_TO_EPILOG $sgpr0

This COPY shouldn't be here in the first place. ISel should insert readfirstlane for this cross bank register move. We have seen similar problems earlier in certain shader test cases at the return.



https://github.com/llvm/llvm-project/pull/128687