[llvm] Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. (PR #127564)

[via llvm-commits]

lakshayk-nv wrote:

> Here's an idea for the tests, for example:
> 
> ```
> $ bin/llvm-exegesis -mcpu=neoverse-v2 --mode=latency --opcode-name=ADDVv16i8v --dump-object-to-disk=t.o
> $ bin/llvm-objdump -d t.o | head
> 
> t.o:    file format elf64-littleaarch64
> 
> Disassembly of section .text:
> 
> 0000000000000000 <foo>:
>        0: 6f00e414      movi    v20.2d, #0000000000000000
>        4: 4e31ba94      addv    b20, v20.16b
>        8: 4e31ba94      addv    b20, v20.16b
>        c: 4e31ba94      addv    b20, v20.16b
> ```
> 
> In other words, can we dump the object file, disassemble and then just match the assembly? This allows us to CHECK: the MOVI instruction, which is a lot clearer than matching a hexidecimal string.
> 
> What do we think?
> 
> I

Seems like good idea.
Added checks for disassembly, It checks for correct setting of register based on generated assembly.
> # FPR128-ASM: {{0|4}}:	{{.*}} movi v{{[0-9]|[1-2][0-9]|3[0-1]}}.2d, {{#0x0|#0000000000000000}}

So, now test case checks for setReg warning, return in assembly snippet and setting of register in assembly; for all four register classes.
Thanks.


https://github.com/llvm/llvm-project/pull/127564