[llvm] 50064db - [AMDGPU] Avoid repeated hash lookups (NFC) (#129189)

[via llvm-commits]

Author: Kazu Hirata
Date: 2025-02-27T22:41:35-08:00
New Revision: 50064db174acf672c7e72e10a72d1302c7aecadd

URL: https://github.com/llvm/llvm-project/commit/50064db174acf672c7e72e10a72d1302c7aecadd
DIFF: https://github.com/llvm/llvm-project/commit/50064db174acf672c7e72e10a72d1302c7aecadd.diff

LOG: [AMDGPU] Avoid repeated hash lookups (NFC) (#129189)

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index f293b3aba7b79..33018ae9677a3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -314,18 +314,20 @@ RegBankLegalizeRules::getRulesForOpc(MachineInstr &MI) const {
       Opc == AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS ||
       Opc == AMDGPU::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS) {
     unsigned IntrID = cast<GIntrinsic>(MI).getIntrinsicID();
-    if (!IRulesAlias.contains(IntrID)) {
+    auto IRAIt = IRulesAlias.find(IntrID);
+    if (IRAIt == IRulesAlias.end()) {
       LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
       llvm_unreachable("No rules defined for intrinsic opcode");
     }
-    return IRules.at(IRulesAlias.at(IntrID));
+    return IRules.at(IRAIt->second);
   }
 
-  if (!GRulesAlias.contains(Opc)) {
+  auto GRAIt = GRulesAlias.find(Opc);
+  if (GRAIt == GRulesAlias.end()) {
     LLVM_DEBUG(dbgs() << "MI: "; MI.dump(););
     llvm_unreachable("No rules defined for generic opcode");
   }
-  return GRules.at(GRulesAlias.at(Opc));
+  return GRules.at(GRAIt->second);
 }
 
 // Syntactic sugar wrapper for predicate lambda that enables '&&', '||' and '!'.