[llvm] a93cda4 - [X86] combineX86ShuffleChain - pull out repeated getOpcode() calls. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 25 05:20:47 PST 2025
Author: Simon Pilgrim
Date: 2025-02-25T13:00:01Z
New Revision: a93cda47ad97af7c69563b3b02dfd9c9a63faefa
URL: https://github.com/llvm/llvm-project/commit/a93cda47ad97af7c69563b3b02dfd9c9a63faefa
DIFF: https://github.com/llvm/llvm-project/commit/a93cda47ad97af7c69563b3b02dfd9c9a63faefa.diff
LOG: [X86] combineX86ShuffleChain - pull out repeated getOpcode() calls. NFC.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 269becb696875..44e070e9fee1f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -39626,6 +39626,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
"Unexpected number of shuffle inputs!");
SDLoc DL(Root);
+ unsigned RootOpc = Root.getOpcode();
MVT RootVT = Root.getSimpleValueType();
unsigned RootSizeInBits = RootVT.getSizeInBits();
unsigned NumRootElts = RootVT.getVectorNumElements();
@@ -39710,7 +39711,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
// optimal than using X86ISD::SHUF128. The insertion is free, even if it has
// to zero the upper subvectors.
if (isUndefOrZeroInRange(Mask, 1, NumBaseMaskElts - 1)) {
- if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR)
+ if (Depth == 0 && RootOpc == ISD::INSERT_SUBVECTOR)
return SDValue(); // Nothing to do!
assert(isInRange(Mask[0], 0, NumBaseMaskElts) &&
"Unexpected lane shuffle");
@@ -39767,7 +39768,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
ScaledMask[1] == (ScaledMask[3] % 2));
if (!isAnyZero(ScaledMask) && !PreferPERMQ) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::SHUF128)
+ if (Depth == 0 && RootOpc == X86ISD::SHUF128)
return SDValue(); // Nothing to do!
MVT ShuffleVT = (FloatDomain ? MVT::v8f64 : MVT::v8i64);
if (SDValue V = MatchSHUF128(ShuffleVT, DL, ScaledMask, V1, V2, DAG))
@@ -39781,7 +39782,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
// than using X86ISD::VPERM2X128. The insertion is free, even if it has to
// zero the upper half.
if (isUndefOrZero(Mask[1])) {
- if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR)
+ if (Depth == 0 && RootOpc == ISD::INSERT_SUBVECTOR)
return SDValue(); // Nothing to do!
assert(isInRange(Mask[0], 0, 2) && "Unexpected lane shuffle");
Res = CanonicalizeShuffleInput(RootVT, V1);
@@ -39795,7 +39796,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
// TODO: Add AVX2 support instead of VPERMQ/VPERMPD.
if (BaseMask[0] == 0 && (BaseMask[1] == 0 || BaseMask[1] == 2) &&
!Subtarget.hasAVX2()) {
- if (Depth == 0 && Root.getOpcode() == ISD::INSERT_SUBVECTOR)
+ if (Depth == 0 && RootOpc == ISD::INSERT_SUBVECTOR)
return SDValue(); // Nothing to do!
SDValue Lo = CanonicalizeShuffleInput(RootVT, V1);
SDValue Hi = CanonicalizeShuffleInput(RootVT, BaseMask[1] == 0 ? V1 : V2);
@@ -39803,7 +39804,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
return insertSubVector(Lo, Hi, NumRootElts / 2, DAG, DL, 128);
}
- if (Depth == 0 && Root.getOpcode() == X86ISD::VPERM2X128)
+ if (Depth == 0 && RootOpc == X86ISD::VPERM2X128)
return SDValue(); // Nothing to do!
// If we have AVX2, prefer to use VPERMQ/VPERMPD for unary shuffles unless
@@ -39820,7 +39821,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
DAG.getUNDEF(RootVT), DAG.getTargetConstant(PermMask, DL, MVT::i8));
}
- if (Depth == 0 && Root.getOpcode() == X86ISD::SHUF128)
+ if (Depth == 0 && RootOpc == X86ISD::SHUF128)
return SDValue(); // Nothing to do!
// TODO - handle AVX512VL cases with X86ISD::SHUF128.
@@ -39903,14 +39904,14 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
if (V1.getValueType() == MaskVT &&
V1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
X86::mayFoldLoad(V1.getOperand(0), Subtarget)) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::VBROADCAST)
+ if (Depth == 0 && RootOpc == X86ISD::VBROADCAST)
return SDValue(); // Nothing to do!
Res = V1.getOperand(0);
Res = DAG.getNode(X86ISD::VBROADCAST, DL, MaskVT, Res);
return DAG.getBitcast(RootVT, Res);
}
if (Subtarget.hasAVX2()) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::VBROADCAST)
+ if (Depth == 0 && RootOpc == X86ISD::VBROADCAST)
return SDValue(); // Nothing to do!
Res = CanonicalizeShuffleInput(MaskVT, V1);
Res = DAG.getNode(X86ISD::VBROADCAST, DL, MaskVT, Res);
@@ -39923,7 +39924,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
DAG, Subtarget, Shuffle, ShuffleSrcVT, ShuffleVT) &&
(!IsMaskedShuffle ||
(NumRootElts == ShuffleVT.getVectorNumElements()))) {
- if (Depth == 0 && Root.getOpcode() == Shuffle)
+ if (Depth == 0 && RootOpc == Shuffle)
return SDValue(); // Nothing to do!
Res = CanonicalizeShuffleInput(ShuffleSrcVT, V1);
Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res);
@@ -39935,7 +39936,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
PermuteImm) &&
(!IsMaskedShuffle ||
(NumRootElts == ShuffleVT.getVectorNumElements()))) {
- if (Depth == 0 && Root.getOpcode() == Shuffle)
+ if (Depth == 0 && RootOpc == Shuffle)
return SDValue(); // Nothing to do!
Res = CanonicalizeShuffleInput(ShuffleVT, V1);
Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res,
@@ -39955,7 +39956,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
if (matchShuffleAsInsertPS(SrcV1, SrcV2, PermuteImm, Zeroable, Mask,
DAG) &&
SrcV2.getOpcode() == ISD::SCALAR_TO_VECTOR) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::INSERTPS)
+ if (Depth == 0 && RootOpc == X86ISD::INSERTPS)
return SDValue(); // Nothing to do!
Res = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32,
CanonicalizeShuffleInput(MVT::v4f32, SrcV1),
@@ -39968,7 +39969,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
isTargetShuffleEquivalent(MaskVT, Mask, {0, 2}, DAG) &&
V2.getOpcode() == ISD::SCALAR_TO_VECTOR &&
V2.getScalarValueSizeInBits() <= 32) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::INSERTPS)
+ if (Depth == 0 && RootOpc == X86ISD::INSERTPS)
return SDValue(); // Nothing to do!
PermuteImm = (/*DstIdx*/ 2 << 4) | (/*SrcIdx*/ 0 << 0);
Res = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32,
@@ -39985,7 +39986,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
NewV2, DL, DAG, Subtarget, Shuffle, ShuffleSrcVT,
ShuffleVT, UnaryShuffle) &&
(!IsMaskedShuffle || (NumRootElts == ShuffleVT.getVectorNumElements()))) {
- if (Depth == 0 && Root.getOpcode() == Shuffle)
+ if (Depth == 0 && RootOpc == Shuffle)
return SDValue(); // Nothing to do!
NewV1 = CanonicalizeShuffleInput(ShuffleSrcVT, NewV1);
NewV2 = CanonicalizeShuffleInput(ShuffleSrcVT, NewV2);
@@ -39999,7 +40000,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
AllowIntDomain, NewV1, NewV2, DL, DAG,
Subtarget, Shuffle, ShuffleVT, PermuteImm) &&
(!IsMaskedShuffle || (NumRootElts == ShuffleVT.getVectorNumElements()))) {
- if (Depth == 0 && Root.getOpcode() == Shuffle)
+ if (Depth == 0 && RootOpc == Shuffle)
return SDValue(); // Nothing to do!
NewV1 = CanonicalizeShuffleInput(ShuffleVT, NewV1);
NewV2 = CanonicalizeShuffleInput(ShuffleVT, NewV2);
@@ -40017,7 +40018,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
uint64_t BitLen, BitIdx;
if (matchShuffleAsEXTRQ(IntMaskVT, V1, V2, Mask, BitLen, BitIdx,
Zeroable)) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::EXTRQI)
+ if (Depth == 0 && RootOpc == X86ISD::EXTRQI)
return SDValue(); // Nothing to do!
V1 = CanonicalizeShuffleInput(IntMaskVT, V1);
Res = DAG.getNode(X86ISD::EXTRQI, DL, IntMaskVT, V1,
@@ -40027,7 +40028,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
}
if (matchShuffleAsINSERTQ(IntMaskVT, V1, V2, Mask, BitLen, BitIdx)) {
- if (Depth == 0 && Root.getOpcode() == X86ISD::INSERTQI)
+ if (Depth == 0 && RootOpc == X86ISD::INSERTQI)
return SDValue(); // Nothing to do!
V1 = CanonicalizeShuffleInput(IntMaskVT, V1);
V2 = CanonicalizeShuffleInput(IntMaskVT, V2);
@@ -40047,7 +40048,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
ShuffleSrcVT.getVectorNumElements();
unsigned Opc =
IsTRUNCATE ? (unsigned)ISD::TRUNCATE : (unsigned)X86ISD::VTRUNC;
- if (Depth == 0 && Root.getOpcode() == Opc)
+ if (Depth == 0 && RootOpc == Opc)
return SDValue(); // Nothing to do!
V1 = CanonicalizeShuffleInput(ShuffleSrcVT, V1);
Res = DAG.getNode(Opc, DL, ShuffleVT, V1);
@@ -40064,9 +40065,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
isSequentialOrUndefInRange(Mask, 0, NumMaskElts, 0, 2)) {
// Bail if this was already a truncation or PACK node.
// We sometimes fail to match PACK if we demand known undef elements.
- if (Depth == 0 && (Root.getOpcode() == ISD::TRUNCATE ||
- Root.getOpcode() == X86ISD::PACKSS ||
- Root.getOpcode() == X86ISD::PACKUS))
+ if (Depth == 0 &&
+ (RootOpc == ISD::TRUNCATE || RootOpc == X86ISD::PACKSS ||
+ RootOpc == X86ISD::PACKUS))
return SDValue(); // Nothing to do!
ShuffleSrcVT = MVT::getIntegerVT(MaskEltSizeInBits * 2);
ShuffleSrcVT = MVT::getVectorVT(ShuffleSrcVT, NumMaskElts / 2);
@@ -40110,8 +40111,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
(Depth >= BWIVPERMV3ShuffleDepth || HasSlowVariableMask);
// If root was a VPERMV/VPERMV3 node, always allow a variable shuffle.
- if ((UnaryShuffle && Root.getOpcode() == X86ISD::VPERMV) ||
- Root.getOpcode() == X86ISD::VPERMV3)
+ if ((UnaryShuffle && RootOpc == X86ISD::VPERMV) || RootOpc == X86ISD::VPERMV3)
AllowVariableCrossLaneMask = AllowVariablePerLaneMask = true;
bool MaskContainsZeros = isAnyZero(Mask);
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