[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Paul Walker via llvm-commits]

paulwalker-arm wrote:

> Hi @paulwalker-arm, it seems that doing this in AArch64LoadStoreOpt won't be a walk in the park as by the time we reach the pass, when compiling with `-msve-vector-bits=128`, it's likely the loads/stores will consist of a mix of LDRs+LD1s/STRs+ST1s as seen [here](https://godbolt.org/z/f3eY9jhGs). We could potentially lower the LD1s/ST1s into LDR/STR before combining them into LDP/STP. Do you think this would be preferable to the current implementation?

I see what you mean, the flaw being the instructions don't support a consistent set of addressing modes?  Fair enough, I think for today that means we're better keeping things simple rather than complicating `AArch64LoadStoreOpt`.  Thanks for investigating.

That just leaves the choice over whether to have this in IR or CodeGen.  Have you looked into doing this as an InstCombine?  I'm hoping doing it in IR will be simpler because there's less corner cases t worry about.

https://github.com/llvm/llvm-project/pull/127500