[llvm] [RISCV] Handle zvbb instructions in getVectorLowDemandedScalarBits. (PR #129011)
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 26 22:27:55 PST 2025
https://github.com/tclin914 created https://github.com/llvm/llvm-project/pull/129011
None
>From 1fe36b8d74b162ea494b668a8ec7aecd173c4e7a Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Thu, 27 Feb 2025 13:34:21 +0800
Subject: [PATCH 1/2] [RISCV] Pre-commit
---
.../CodeGen/RISCV/rvv/zvbb-demanded-bits.ll | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
new file mode 100644
index 0000000000000..09120d73da170
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
@@ -0,0 +1,63 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvbb,+prefer-w-inst \
+; RUN: -verify-machineinstrs | FileCheck %s
+
+define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
+; CHECK-LABEL: vrol_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vrol.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %s = add i8 %b, 1
+ %b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 0
+ %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ %x = call <vscale x 1 x i8> @llvm.fshl.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
+ ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
+; CHECK-LABEL: vror_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vror.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %s = add i8 %b, 1
+ %b.head = insertelement <vscale x 1 x i8> poison, i8 %s, i32 0
+ %b.splat = shufflevector <vscale x 1 x i8> %b.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ %x = call <vscale x 1 x i8> @llvm.fshr.nxv1i8(<vscale x 1 x i8> %a, <vscale x 1 x i8> %a, <vscale x 1 x i8> %b.splat)
+ ret <vscale x 1 x i8> %x
+}
+
+define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {
+; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-NEXT: vwsll.vx v10, v8, a0
+; CHECK-NEXT: vmv2r.v v8, v10
+; CHECK-NEXT: ret
+ %s = add i8 %b, 1
+ %head = insertelement <vscale x 2 x i8> poison, i8 %s, i32 0
+ %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
+ %x = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
+ %y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
+ %z = shl <vscale x 2 x i64> %x, %y
+ ret <vscale x 2 x i64> %z
+}
+
+define <vscale x 1 x i8> @vandn_vx_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {
+; CHECK-LABEL: vandn_vx_nxv1i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; CHECK-NEXT: vandn.vx v8, v8, a0
+; CHECK-NEXT: ret
+ %s = add i8 %x, 1
+ %a = xor i8 %s, -1
+ %head = insertelement <vscale x 1 x i8> poison, i8 %a, i32 0
+ %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
+ %b = and <vscale x 1 x i8> %splat, %y
+ ret <vscale x 1 x i8> %b
+}
>From c0ffdf303d343e4ea76018e39e29355d1c9a56ca Mon Sep 17 00:00:00 2001
From: Jim Lin <jim at andestech.com>
Date: Wed, 12 Feb 2025 09:15:42 +0800
Subject: [PATCH 2/2] [RISCV] Handle zvbb instructions in
getVectorLowDemandedScalarBits.
---
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 +++++++-
llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll | 8 ++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index bca508e2136ab..913169c00b642 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -4107,7 +4107,6 @@ bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) {
std::optional<unsigned>
RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
- // TODO: Handle Zvbb instructions
switch (Opcode) {
default:
return std::nullopt;
@@ -4119,6 +4118,9 @@ RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
// 12.4. Vector Single-Width Scaling Shift Instructions
case RISCV::VSSRL_VX:
case RISCV::VSSRA_VX:
+ // Zvbb
+ case RISCV::VROL_VX:
+ case RISCV::VROR_VX:
// Only the low lg2(SEW) bits of the shift-amount value are used.
return Log2SEW;
@@ -4128,6 +4130,8 @@ RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
case RISCV::VNCLIPU_WX:
case RISCV::VNCLIP_WX:
+ // Zvbb
+ case RISCV::VWSLL_VX:
// Only the low lg2(2*SEW) bits of the shift-amount value are used.
return Log2SEW + 1;
@@ -4213,6 +4217,8 @@ RISCV::getVectorLowDemandedScalarBits(uint16_t Opcode, unsigned Log2SEW) {
case RISCV::VSMUL_VX:
// 16.1. Integer Scalar Move Instructions
case RISCV::VMV_S_X:
+ // Zvbb
+ case RISCV::VANDN_VX:
return 1U << Log2SEW;
}
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll b/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
index 09120d73da170..4d548749805dc 100644
--- a/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/zvbb-demanded-bits.ll
@@ -5,7 +5,7 @@
define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
; CHECK-LABEL: vrol_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vrol.vx v8, v8, a0
; CHECK-NEXT: ret
@@ -19,7 +19,7 @@ define <vscale x 1 x i8> @vrol_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
; CHECK-LABEL: vror_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vror.vx v8, v8, a0
; CHECK-NEXT: ret
@@ -33,7 +33,7 @@ define <vscale x 1 x i8> @vror_vx_nxv1i8(<vscale x 1 x i8> %a, i8 %b) {
define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b) {
; CHECK-LABEL: vwsll_vx_i8_nxv2i64_zext:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vwsll.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
@@ -50,7 +50,7 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b
define <vscale x 1 x i8> @vandn_vx_nxv1i8(i8 %x, <vscale x 1 x i8> %y) {
; CHECK-LABEL: vandn_vx_nxv1i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: addi a0, a0, 1
+; CHECK-NEXT: addiw a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vandn.vx v8, v8, a0
; CHECK-NEXT: ret
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