[llvm] [AArch64][SVE] Lower unpredicated loads/stores as fixed LDR/STR with -msve-vector-bits=128. (PR #127500)

[Ricardo Jesus via llvm-commits]

rj-jesus wrote:

> I see what you mean, the flaw being the instructions don't support a consistent set of addressing modes?

Exactly, this seems to be a (likely unintended) side-effect of compiling for VLS SVE. When compiling for VLS SVE, VL-based offsets are folded to constants early on, which then leads to a mismatch with the addressing modes of SVE loads/stores given they generally expect offsets as multiples of VL ([example](https://godbolt.org/z/5qTEKWG5b)). I think it would be worth "uplifting" these offsets back into multiples of VL, such that they could be folded into immediate-VL-based loads/stores, though I'm not sure where would be the best place to do this. Do you think this is worth trying, probably independently from this PR?

> That just leaves the choice over whether to have this in IR or CodeGen. Have you looked into doing this as an InstCombine?

I haven't tried this yet as I wanted to limit this to the cases we knew we could fold to Neon LDR/STR to promote LDP/STP merging, though I think we could accomplish the same thing with an extra hook that would inspect the vector type and decide accordingly. Is that what you had in mind?

https://github.com/llvm/llvm-project/pull/127500