[llvm] a085da6 - [RISCV] Remove X26 from encodeRlist. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2025-02-28T15:38:34-08:00
New Revision: a085da66783e9576f9a9105e7fd5726f2039303b

URL: https://github.com/llvm/llvm-project/commit/a085da66783e9576f9a9105e7fd5726f2039303b
DIFF: https://github.com/llvm/llvm-project/commit/a085da66783e9576f9a9105e7fd5726f2039303b.diff

LOG: [RISCV] Remove X26 from encodeRlist. NFC

The caller already checks X26 and generates its own error.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 85d53f0c5045c..541979a0f70e8 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2753,8 +2753,7 @@ ParseStatus RISCVAsmParser::parseReglist(OperandVector &Operands) {
     RegEnd = RegStart;
 
   auto Encode = RISCVZC::encodeRlist(RegEnd, IsEABI);
-  if (Encode == RISCVZC::INVALID_RLIST)
-    return Error(S, "invalid register list");
+  assert(Encode != RISCVZC::INVALID_RLIST);
   Operands.push_back(RISCVOperand::createRlist(Encode, S));
 
   return ParseStatus::Success;

diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index b2b604ff83719..185a5d8a9c9b2 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -617,8 +617,6 @@ inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
     return RLISTENCODE::RA_S0_S8;
   case RISCV::X25:
     return RLISTENCODE::RA_S0_S9;
-  case RISCV::X26:
-    return RLISTENCODE::INVALID_RLIST;
   case RISCV::X27:
     return RLISTENCODE::RA_S0_S11;
   default: