[llvm] a70175a - [CodeGen] Use MCRegister and Register. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Mar 2 22:34:56 PST 2025
Author: Craig Topper
Date: 2025-03-02T22:33:26-08:00
New Revision: a70175ab932412ac7d46f3c82cd19384c33fc868
URL: https://github.com/llvm/llvm-project/commit/a70175ab932412ac7d46f3c82cd19384c33fc868
DIFF: https://github.com/llvm/llvm-project/commit/a70175ab932412ac7d46f3c82cd19384c33fc868.diff
LOG: [CodeGen] Use MCRegister and Register. NFC
Added:
Modified:
llvm/include/llvm/CodeGen/LiveInterval.h
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/CodeGen/PHIElimination.cpp
llvm/lib/CodeGen/PHIEliminationUtils.cpp
llvm/lib/CodeGen/PHIEliminationUtils.h
llvm/lib/CodeGen/ReachingDefAnalysis.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/SplitKit.cpp
llvm/lib/CodeGen/StackMaps.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LiveInterval.h b/llvm/include/llvm/CodeGen/LiveInterval.h
index 236a439b80a24..abef3eb24f79a 100644
--- a/llvm/include/llvm/CodeGen/LiveInterval.h
+++ b/llvm/include/llvm/CodeGen/LiveInterval.h
@@ -720,7 +720,7 @@ namespace llvm {
void incrementWeight(float Inc) { Weight += Inc; }
void setWeight(float Value) { Weight = Value; }
- LiveInterval(unsigned Reg, float Weight) : Reg(Reg), Weight(Weight) {}
+ LiveInterval(Register Reg, float Weight) : Reg(Reg), Weight(Weight) {}
~LiveInterval() {
clearSubRanges();
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index caec0524e7ab6..24c6dafc60459 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -111,7 +111,7 @@ class SSAIfConv {
/// Information about each phi in the Tail block.
struct PHIInfo {
MachineInstr *PHI;
- unsigned TReg = 0, FReg = 0;
+ Register TReg, FReg;
// Latencies from Cond+Branch, TReg, and FReg to DstReg.
int CondCycles = 0, TCycles = 0, FCycles = 0;
@@ -522,8 +522,8 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) {
if (PI.PHI->getOperand(i+1).getMBB() == FPred)
PI.FReg = PI.PHI->getOperand(i).getReg();
}
- assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI");
- assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");
+ assert(PI.TReg.isVirtual() && "Bad PHI");
+ assert(PI.FReg.isVirtual() && "Bad PHI");
// Get target information.
if (!TII->canInsertSelect(*Head, Cond, PI.PHI->getOperand(0).getReg(),
@@ -645,7 +645,7 @@ void SSAIfConv::rewritePHIOperands() {
// Convert all PHIs to select instructions inserted before FirstTerm.
for (PHIInfo &PI : PHIs) {
- unsigned DstReg = 0;
+ Register DstReg;
LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index 79085e587ebc4..0e7571bbf5ab1 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -587,7 +587,7 @@ class LiveDebugVariables::LDVImpl {
SmallVector<std::unique_ptr<UserLabel>, 2> userLabels;
/// Map virtual register to eq class leader.
- using VRMap = DenseMap<unsigned, UserValue *>;
+ using VRMap = DenseMap<Register, UserValue *>;
VRMap virtRegToEqClass;
/// Map to find existing UserValue instances.
diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp
index 00dae84b5840b..d50b7c0c24f86 100644
--- a/llvm/lib/CodeGen/LiveVariables.cpp
+++ b/llvm/lib/CodeGen/LiveVariables.cpp
@@ -852,7 +852,7 @@ void LiveVariables::addNewBlock(MachineBasicBlock *BB,
MachineBasicBlock *SuccBB) {
const unsigned NumNew = BB->getNumber();
- DenseSet<unsigned> Defs, Kills;
+ DenseSet<Register> Defs, Kills;
MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
for (; BBI != BBE && BBI->isPHI(); ++BBI) {
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 789c628a64a23..96ba475f93844 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -191,7 +191,7 @@ template <> struct BlockScalarTraits<Module> {
} // end namespace yaml
} // end namespace llvm
-static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
+static void printRegMIR(Register Reg, yaml::StringValue &Dest,
const TargetRegisterInfo *TRI) {
raw_string_ostream OS(Dest.Value);
OS << printReg(Reg, TRI);
@@ -299,7 +299,7 @@ static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
OS << ')';
}
-static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
+static void printRegClassOrBank(Register Reg, yaml::StringValue &Dest,
const MachineRegisterInfo &RegInfo,
const TargetRegisterInfo *TRI) {
raw_string_ostream OS(Dest.Value);
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index e90b224c98ddb..b3a71d1144726 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1773,7 +1773,7 @@ MachineBasicBlock::liveout_iterator MachineBasicBlock::liveout_begin() const {
"Liveness information is accurate");
const TargetLowering &TLI = *MF.getSubtarget().getTargetLowering();
- MCPhysReg ExceptionPointer = 0, ExceptionSelector = 0;
+ MCRegister ExceptionPointer, ExceptionSelector;
if (MF.getFunction().hasPersonalityFn()) {
auto PersonalityFn = MF.getFunction().getPersonalityFn();
ExceptionPointer = TLI.getExceptionPointerRegister(PersonalityFn);
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index bea0eaf206f5e..b70d50ce2d8ba 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -91,7 +91,7 @@ class MachineCSEImpl {
ScopedHashTable<MachineInstr *, unsigned, MachineInstrExpressionTrait,
AllocatorTy>;
using ScopeType = ScopedHTType::ScopeTy;
- using PhysDefVector = SmallVector<std::pair<unsigned, unsigned>, 2>;
+ using PhysDefVector = SmallVector<std::pair<unsigned, Register>, 2>;
unsigned LookAheadLimit = 0;
DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
@@ -321,7 +321,7 @@ bool MachineCSEImpl::hasLivePhysRegDefUses(const MachineInstr *MI,
// common since this pass is run before livevariables. We can scan
// forward a few instructions and check if it is obviously dead.
if (!MO.isDead() && !isPhysDefTriviallyDead(Reg.asMCReg(), I, MBB->end()))
- PhysDefs.push_back(std::make_pair(MOP.index(), Reg));
+ PhysDefs.emplace_back(MOP.index(), Reg);
}
// Finally, add all defs to PhysRefs as well.
@@ -531,9 +531,9 @@ void MachineCSEImpl::ExitScope(MachineBasicBlock *MBB) {
bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
bool Changed = false;
- SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
+ SmallVector<std::pair<Register, Register>, 8> CSEPairs;
SmallVector<unsigned, 2> ImplicitDefsToUpdate;
- SmallVector<unsigned, 2> ImplicitDefs;
+ SmallVector<Register, 2> ImplicitDefs;
for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
if (!isCSECandidate(&MI))
continue;
@@ -667,15 +667,15 @@ bool MachineCSEImpl::ProcessBlockCSE(MachineBasicBlock *MBB) {
break;
}
- CSEPairs.push_back(std::make_pair(OldReg, NewReg));
+ CSEPairs.emplace_back(OldReg, NewReg);
--NumDefs;
}
// Actually perform the elimination.
if (DoCSE) {
- for (const std::pair<unsigned, unsigned> &CSEPair : CSEPairs) {
- unsigned OldReg = CSEPair.first;
- unsigned NewReg = CSEPair.second;
+ for (const std::pair<Register, Register> &CSEPair : CSEPairs) {
+ Register OldReg = CSEPair.first;
+ Register NewReg = CSEPair.second;
// OldReg may have been unused but is used now, clear the Dead flag
MachineInstr *Def = MRI->getUniqueVRegDef(NewReg);
assert(Def != nullptr && "CSEd register has no unique definition?");
diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
index 021c1a058c020..ffe52d6d60b7c 100644
--- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp
+++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp
@@ -680,9 +680,9 @@ struct DataDep {
: DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {}
/// Create a DataDep from an SSA form virtual register.
- DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
- : UseOp(UseOp) {
- assert(Register::isVirtualRegister(VirtReg));
+ DataDep(const MachineRegisterInfo *MRI, Register VirtReg, unsigned UseOp)
+ : UseOp(UseOp) {
+ assert(VirtReg.isVirtual());
MachineOperand *DefMO = MRI->getOneDef(VirtReg);
assert(DefMO && "Register does not have unique def");
DefMI = DefMO->getParent();
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index b71e5b8538689..14f91a87f75b4 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -110,7 +110,7 @@ class PHIEliminationImpl {
// Map reusable lowered PHI node -> incoming join register.
using LoweredPHIMap =
- DenseMap<MachineInstr *, unsigned, MachineInstrExpressionTrait>;
+ DenseMap<MachineInstr *, Register, MachineInstrExpressionTrait>;
LoweredPHIMap LoweredPHIs;
MachineFunctionPass *P = nullptr;
@@ -321,7 +321,7 @@ bool PHIEliminationImpl::EliminatePHINodes(MachineFunction &MF,
/// Return true if all defs of VirtReg are implicit-defs.
/// This includes registers with no defs.
-static bool isImplicitlyDefined(unsigned VirtReg,
+static bool isImplicitlyDefined(Register VirtReg,
const MachineRegisterInfo &MRI) {
for (MachineInstr &DI : MRI.def_instructions(VirtReg))
if (!DI.isImplicitDef())
@@ -357,7 +357,7 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
// Create a new register for the incoming PHI arguments.
MachineFunction &MF = *MBB.getParent();
- unsigned IncomingReg = 0;
+ Register IncomingReg;
bool EliminateNow = true; // delay elimination of nodes in LoweredPHIs
bool reusedIncoming = false; // Is IncomingReg reused from an earlier PHI?
@@ -376,7 +376,7 @@ void PHIEliminationImpl::LowerPHINode(MachineBasicBlock &MBB,
// typically those created by tail duplication. Typically, an identical PHI
// node can't occur, so avoid hashing/storing such PHIs, which is somewhat
// expensive.
- unsigned *Entry = nullptr;
+ Register *Entry = nullptr;
if (AllEdgesCritical)
Entry = &LoweredPHIs[MPhi];
if (Entry && *Entry) {
diff --git a/llvm/lib/CodeGen/PHIEliminationUtils.cpp b/llvm/lib/CodeGen/PHIEliminationUtils.cpp
index 016335f420d3e..f4562f437788e 100644
--- a/llvm/lib/CodeGen/PHIEliminationUtils.cpp
+++ b/llvm/lib/CodeGen/PHIEliminationUtils.cpp
@@ -19,7 +19,7 @@ using namespace llvm;
// the basic block.
MachineBasicBlock::iterator
llvm::findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB,
- unsigned SrcReg) {
+ Register SrcReg) {
// Handle the trivial case trivially.
if (MBB->empty())
return MBB->begin();
diff --git a/llvm/lib/CodeGen/PHIEliminationUtils.h b/llvm/lib/CodeGen/PHIEliminationUtils.h
index 0ff3a41f47d30..b654b7d30f6b9 100644
--- a/llvm/lib/CodeGen/PHIEliminationUtils.h
+++ b/llvm/lib/CodeGen/PHIEliminationUtils.h
@@ -18,7 +18,7 @@ namespace llvm {
/// might jump out of the basic block.
MachineBasicBlock::iterator
findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB,
- unsigned SrcReg);
+ Register SrcReg);
}
#endif
diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
index 59ad9ffae5bf9..415674231b5cb 100644
--- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
+++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp
@@ -646,7 +646,7 @@ bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From,
if (From->getParent() != To->getParent() || From == To)
return false;
- SmallSet<int, 2> Defs;
+ SmallSet<Register, 2> Defs;
// First check that From would compute the same value if moved.
for (auto &MO : From->operands()) {
if (!isValidReg(MO))
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index 58f212e1ba521..6c297cd88ddbb 100644
--- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
+++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
@@ -218,7 +218,7 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
const SmallVectorImpl<SubRangeInfo> &SubRangeInfos,
const SmallVectorImpl<LiveInterval*> &Intervals) const {
const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
- unsigned Reg = Intervals[0]->reg();
+ Register Reg = Intervals[0]->reg();
for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg),
E = MRI->reg_nodbg_end(); I != E; ) {
MachineOperand &MO = *I++;
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index 5a724805243fd..f6e73e24d1bb9 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -814,7 +814,7 @@ SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
return VNI->def;
}
-static bool hasTiedUseOf(MachineInstr &MI, unsigned Reg) {
+static bool hasTiedUseOf(MachineInstr &MI, Register Reg) {
return any_of(MI.defs(), [Reg](const MachineOperand &MO) {
return MO.isReg() && MO.isTied() && MO.getReg() == Reg;
});
@@ -1405,7 +1405,8 @@ void SplitEditor::rewriteAssigned(bool ExtendRanges) {
assert(LI.hasSubRanges());
LiveIntervalCalc SubLIC;
- Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
+ Register Reg = EP.MO.getReg();
+ unsigned Sub = EP.MO.getSubReg();
LaneBitmask LM = Sub != 0 ? TRI.getSubRegIndexLaneMask(Sub)
: MRI.getMaxLaneMaskForVReg(Reg);
for (LiveInterval::SubRange &S : LI.subranges()) {
diff --git a/llvm/lib/CodeGen/StackMaps.cpp b/llvm/lib/CodeGen/StackMaps.cpp
index 7480963c1f521..eb6dd67dba576 100644
--- a/llvm/lib/CodeGen/StackMaps.cpp
+++ b/llvm/lib/CodeGen/StackMaps.cpp
@@ -191,7 +191,7 @@ unsigned StackMaps::getNextMetaArgIdx(const MachineInstr *MI, unsigned CurIdx) {
}
/// Go up the super-register chain until we hit a valid dwarf register number.
-static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
+static unsigned getDwarfRegNum(MCRegister Reg, const TargetRegisterInfo *TRI) {
int RegNum;
for (MCPhysReg SR : TRI->superregs_inclusive(Reg)) {
RegNum = TRI->getDwarfRegNum(SR, false);
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