[llvm] [RISCV] Move VMV0 elimination past machine SSA opts (PR #126850)

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Wed Feb 26 07:42:30 PST 2025

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newgre wrote:

I've rebuilt the compiler and re-ran the test and with your fix included, the ICE goes away. Thanks!

https://github.com/llvm/llvm-project/pull/126850

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