[llvm] [AMDGPU] Simplify conditional expressions. NFC. (PR #129228)
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llvm-commits at lists.llvm.org
Fri Feb 28 03:25:22 PST 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Jay Foad (jayfoad)
<details>
<summary>Changes</summary>
Simplfy `cond ? val : false` to `cond && val` and similar.
---
Full diff: https://github.com/llvm/llvm-project/pull/129228.diff
9 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (+2-2)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIISelLowering.cpp (+2-4)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+1-1)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+15-15)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index 1cb1c75154a97..fdba8835cbf0a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -404,8 +404,8 @@ bool AMDGPUCodeGenPrepareImpl::isSigned(const BinaryOperator &I) const {
}
bool AMDGPUCodeGenPrepareImpl::isSigned(const SelectInst &I) const {
- return isa<ICmpInst>(I.getOperand(0)) ?
- cast<ICmpInst>(I.getOperand(0))->isSigned() : false;
+ return isa<ICmpInst>(I.getOperand(0)) &&
+ cast<ICmpInst>(I.getOperand(0))->isSigned();
}
bool AMDGPUCodeGenPrepareImpl::needsPromotionToI32(const Type *T) const {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 2d46cf3b70a34..ade81f17ecca5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1041,7 +1041,7 @@ bool AMDGPUTargetLowering::isNarrowingProfitable(SDNode *N, EVT SrcVT,
case ISD::SETCC:
case ISD::SELECT:
if (Subtarget->has16BitInsts() &&
- (DestVT.isVector() ? !Subtarget->hasVOP3PInsts() : true)) {
+ (!DestVT.isVector() || !Subtarget->hasVOP3PInsts())) {
// Don't narrow back down to i16 if promoted to i32 already.
if (!N->isDivergent() && DestVT.isInteger() &&
DestVT.getScalarSizeInBits() > 1 &&
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index a787c10a9421c..c59fb411124c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2003,9 +2003,9 @@ static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE,
if (TexFailCtrl)
IsTexFail = true;
- TFE = (TexFailCtrl & 0x1) ? true : false;
+ TFE = TexFailCtrl & 0x1;
TexFailCtrl &= ~(uint64_t)0x1;
- LWE = (TexFailCtrl & 0x2) ? true : false;
+ LWE = TexFailCtrl & 0x2;
TexFailCtrl &= ~(uint64_t)0x2;
return TexFailCtrl == 0;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
index 28016b5936ccf..226044c892b9e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
@@ -308,7 +308,7 @@ bool AMDGPUPromoteAllocaImpl::run(Function &F, bool PromoteToLDS) {
MaxVGPRs = getMaxVGPRs(TM, F);
- bool SufficientLDS = PromoteToLDS ? hasSufficientLocalMem(F) : false;
+ bool SufficientLDS = PromoteToLDS && hasSufficientLocalMem(F);
// Use up to 1/4 of available register budget for vectorization.
// FIXME: Increase the limit for whole function budgets? Perhaps x2?
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
index 3159b497a1ecb..6ba7920e9f00c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp
@@ -378,7 +378,7 @@ void AMDGPUSwLowerLDS::buildSwDynLDSGlobal(Function *Func) {
void AMDGPUSwLowerLDS::populateSwLDSAttributeAndMetadata(Function *Func) {
auto &LDSParams = FuncLDSAccessInfo.KernelToLDSParametersMap[Func];
- bool IsDynLDSUsed = LDSParams.SwDynLDS ? true : false;
+ bool IsDynLDSUsed = LDSParams.SwDynLDS;
uint32_t Offset = LDSParams.LDSSize;
recordLDSAbsoluteAddress(M, LDSParams.SwLDS, 0);
addLDSSizeAttribute(Func, Offset, IsDynLDSUsed);
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index fc33648bf1416..df6d414a93b1e 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -15334,10 +15334,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
unsigned NewDmask = 0;
unsigned TFEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::tfe) - 1;
unsigned LWEIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::lwe) - 1;
- bool UsesTFC = ((int(TFEIdx) >= 0 && Node->getConstantOperandVal(TFEIdx)) ||
- (int(LWEIdx) >= 0 && Node->getConstantOperandVal(LWEIdx)))
- ? true
- : false;
+ bool UsesTFC = (int(TFEIdx) >= 0 && Node->getConstantOperandVal(TFEIdx)) ||
+ (int(LWEIdx) >= 0 && Node->getConstantOperandVal(LWEIdx));
unsigned TFCLane = 0;
bool HasChain = Node->getNumValues() > 1;
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 6f99c7b4c4962..7d6990c097774 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3500,7 +3500,7 @@ bool SIRegisterInfo::isSGPRReg(const MachineRegisterInfo &MRI,
RC = MRI.getRegClass(Reg);
else
RC = getPhysRegBaseClass(Reg);
- return RC ? isSGPRClass(RC) : false;
+ return RC && isSGPRClass(RC);
}
const TargetRegisterClass *
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 6a92e54b69edc..b51cf536467b9 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -459,17 +459,17 @@ int getMTBUFElements(unsigned Opc) {
bool getMTBUFHasVAddr(unsigned Opc) {
const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
- return Info ? Info->has_vaddr : false;
+ return Info && Info->has_vaddr;
}
bool getMTBUFHasSrsrc(unsigned Opc) {
const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
- return Info ? Info->has_srsrc : false;
+ return Info && Info->has_srsrc;
}
bool getMTBUFHasSoffset(unsigned Opc) {
const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
- return Info ? Info->has_soffset : false;
+ return Info && Info->has_soffset;
}
int getMUBUFBaseOpcode(unsigned Opc) {
@@ -489,47 +489,47 @@ int getMUBUFElements(unsigned Opc) {
bool getMUBUFHasVAddr(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->has_vaddr : false;
+ return Info && Info->has_vaddr;
}
bool getMUBUFHasSrsrc(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->has_srsrc : false;
+ return Info && Info->has_srsrc;
}
bool getMUBUFHasSoffset(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->has_soffset : false;
+ return Info && Info->has_soffset;
}
bool getMUBUFIsBufferInv(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->IsBufferInv : false;
+ return Info && Info->IsBufferInv;
}
bool getMUBUFTfe(unsigned Opc) {
const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
- return Info ? Info->tfe : false;
+ return Info && Info->tfe;
}
bool getSMEMIsBuffer(unsigned Opc) {
const SMInfo *Info = getSMEMOpcodeHelper(Opc);
- return Info ? Info->IsBuffer : false;
+ return Info && Info->IsBuffer;
}
bool getVOP1IsSingle(unsigned Opc) {
const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
- return Info ? Info->IsSingle : true;
+ return !Info || Info->IsSingle;
}
bool getVOP2IsSingle(unsigned Opc) {
const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
- return Info ? Info->IsSingle : true;
+ return !Info || Info->IsSingle;
}
bool getVOP3IsSingle(unsigned Opc) {
const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
- return Info ? Info->IsSingle : true;
+ return !Info || Info->IsSingle;
}
bool isVOPC64DPP(unsigned Opc) {
@@ -540,12 +540,12 @@ bool isVOPCAsmOnly(unsigned Opc) { return isVOPCAsmOnlyOpcodeHelper(Opc); }
bool getMAIIsDGEMM(unsigned Opc) {
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
- return Info ? Info->is_dgemm : false;
+ return Info && Info->is_dgemm;
}
bool getMAIIsGFX940XDL(unsigned Opc) {
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
- return Info ? Info->is_gfx940_xdl : false;
+ return Info && Info->is_gfx940_xdl;
}
uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal) {
@@ -666,7 +666,7 @@ bool isGenericAtomic(unsigned Opc) {
bool isTrue16Inst(unsigned Opc) {
const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
- return Info ? Info->IsTrue16 : false;
+ return Info && Info->IsTrue16;
}
FPType getFPDstSelType(unsigned Opc) {
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
index 99ea929ea93fe..b05696d2dfa05 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp
@@ -452,7 +452,7 @@ bool AMDGPUMCKernelCodeT::ParseKernelCodeT(StringRef ID, MCAsmParser &MCParser,
return true;
}
auto Parser = getParserTable()[Idx];
- return Parser ? Parser(*this, MCParser, Err) : false;
+ return Parser && Parser(*this, MCParser, Err);
}
void AMDGPUMCKernelCodeT::EmitKernelCodeT(raw_ostream &OS, MCContext &Ctx,
``````````
</details>
https://github.com/llvm/llvm-project/pull/129228
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