[llvm] [RISCV] Intrinsic Support for XCVelw (PR #129168)

[via llvm-commits]

https://github.com/realqhc updated https://github.com/llvm/llvm-project/pull/129168

>From 6bcead8f9b2304d03384336072eb8ca2e2c30944 Mon Sep 17 00:00:00 2001
From: Qihan Cai <caiqihan021 at hotmail.com>
Date: Fri, 28 Feb 2025 12:20:48 +1100
Subject: [PATCH 1/2] [RISCV] Intrinsic Support for XCVelw Add intrinsic
 support for XCVelw extension.

Documentation: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html#event-load-instruction
---
 llvm/include/llvm/IR/IntrinsicsRISCVXCV.td    |  3 +++
 .../Target/RISCV/AsmParser/RISCVAsmParser.cpp |  3 +++
 llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td    |  7 +++++
 llvm/test/CodeGen/RISCV/xcvelw.ll             | 27 +++++++++++++++++++
 4 files changed, 40 insertions(+)
 create mode 100644 llvm/test/CodeGen/RISCV/xcvelw.ll

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
index 6e7e90438c621..2d923885ebec6 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
@@ -90,4 +90,7 @@ let TargetPrefix = "riscv" in {
   def int_riscv_cv_mac_machhuRN : ScalarCoreVMacGprGprGprImmIntrinsic;
   def int_riscv_cv_mac_macsRN   : ScalarCoreVMacGprGprGprImmIntrinsic;
   def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
+
+  def int_riscv_cv_elw_elw
+    : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
 } // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 36e2fa0262f9d..c637c427584a7 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -3919,6 +3919,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
 
     return false;
   }
+  case RISCV::PseudoCV_ELW:
+    emitLoadStoreSymbol(Inst, RISCV::CV_ELW, IDLoc, Out, /*HasTmpReg=*/false);
+    return false;
   }
 
   emitToStreamer(Out, Inst);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index bade4863ad348..84b181cfda0cf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -662,6 +662,7 @@ class CVLoad_ri<bits<3> funct3, string opcodestr>
 
 let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
     mayLoad = 1, mayStore = 0 in {
+  def PseudoCV_ELW : PseudoLoad<"cv.elw">;
   // Event load
   def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
 }
@@ -707,6 +708,12 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStrrPat<store, CV_SW_rr>;
 }
 
+let Predicates = [HasVendorXCVelw, IsRV32] in {
+  def : Pat<(int_riscv_cv_elw_elw (XLenVT GPR:$rs1)), (PseudoCV_ELW GPR:$rs1)>;
+  def : Pat<(int_riscv_cv_elw_elw (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
+            (CV_ELW GPR:$rs1, simm12:$imm12)>;
+}
+
 def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
 def cv_tuimm5 : TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
 def cv_uimm10 : ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
diff --git a/llvm/test/CodeGen/RISCV/xcvelw.ll b/llvm/test/CodeGen/RISCV/xcvelw.ll
new file mode 100644
index 0000000000000..4ff8a5b38494f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xcvelw.ll
@@ -0,0 +1,27 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -O0 -mtriple=riscv32 -mattr=+xcvelw -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+declare i32 @llvm.riscv.cv.elw.elw(i8*)
+
+define i32 @test.cv.elw.elw(i8* %a) {
+; CHECK-LABEL: test.cv.elw.elw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cv.elw a0, 0(a0)
+; CHECK-NEXT:    ret
+  %1 = call i32 @llvm.riscv.cv.elw.elw(i8* %a)
+  ret i32 %1
+}
+
+define i32 @test.cv.elw.elw2(i8* %a, i32 %b) {
+; CHECK-LABEL: test.cv.elw.elw2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    cv.elw a0, 7(a0)
+; CHECK-NEXT:    ret
+  %c = add i32 %b, 4
+  %d = add i32 %c, 3
+  %e = getelementptr i8, i8* %a, i32 %d
+  %1 = call i32 @llvm.riscv.cv.elw.elw(i8* %e)
+  ret i32 %1
+}
\ No newline at end of file

>From 33baae6a23a8eb22aac2b0422ef8f1c173331b96 Mon Sep 17 00:00:00 2001
From: Qihan Cai <caiqihan021 at hotmail.com>
Date: Fri, 28 Feb 2025 16:14:05 +1100
Subject: [PATCH 2/2] add side effects to this instruction

---
 llvm/include/llvm/IR/IntrinsicsRISCVXCV.td | 3 ++-
 llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
index 2d923885ebec6..e4da92292fe41 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXCV.td
@@ -92,5 +92,6 @@ let TargetPrefix = "riscv" in {
   def int_riscv_cv_mac_machhsRN : ScalarCoreVMacGprGprGprImmIntrinsic;
 
   def int_riscv_cv_elw_elw
-    : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+    : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty],
+                [IntrReadMem, IntrArgMemOnly, IntrHasSideEffects]>;
 } // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 84b181cfda0cf..dcdf8f928e723 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -660,7 +660,7 @@ class CVLoad_ri<bits<3> funct3, string opcodestr>
     : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
       (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
 
-let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 0, 
+let Predicates = [HasVendorXCVelw, IsRV32], hasSideEffects = 1,
     mayLoad = 1, mayStore = 0 in {
   def PseudoCV_ELW : PseudoLoad<"cv.elw">;
   // Event load