[clang] [llvm] [RISCV][MC] Implement MC for Base P extension (PR #123271)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 27 15:26:10 PST 2025
================
@@ -0,0 +1,1050 @@
+//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the standard 'Base P'
+// Packed SIMD instruction set extension.
+//
+// This version is still experimental as the 'P' extension hasn't been
+// ratified yet.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def RVPGPRPairRV32 : RegisterOperand<GPRPair> {
+ let ParserMatchClass = GPRPairRV32Operand;
+ let EncoderMethod = "getRVPGPRPair";
+ let DecoderMethod = "decodeRVPGPRPair";
+}
+
+def simm10 : RISCVSImmLeafOp<10> {
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (!MCOp.evaluateAsConstantImm(Imm))
+ return false;
+ return isInt<10>(Imm);
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnary<bits<5> funct5, bits<7> wuimm,
+ bits<3> funct3, RISCVOpcode opcode,
+ string opcodestr>
+ : RVInstIBase<funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let Inst{31-27} = funct5;
+ let Inst{26-20} = wuimm;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm9<bits<7> funct7, string opcodestr, DAGOperand TyRd = GPR>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs TyRd:$rd), (ins simm10:$simm10),
+ opcodestr, "$rd, $simm10"> {
+ bits<10> simm10;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-15} = simm10;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryImm8<bits<8> funct8, string opcodestr, DAGOperand TyRd = GPR>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs TyRd:$rd), (ins uimm8:$uimm8),
+ opcodestr, "$rd, $uimm8"> {
+ bits<8> uimm8;
+ let Inst{31-24} = funct8;
+ let Inst{23-16} = uimm8;
+ let Inst{15} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let Inst{31-27} = 0b11100;
+ let Inst{26-25} = w;
+ let Inst{24-20} = uf;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryWUFRs1pRdp<bits<2> w, bits<5> uf, string opcodestr>
+ : RVInstIBase<0b010, OPC_OP_IMM_32, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p), opcodestr, "$rdp, $rs1p"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{31-27} = 0b01100;
+ let Inst{26-25} = w;
+ let Inst{24-20} = uf;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = 0b0;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPUnaryF<bit bfr, bits<3> f, bit aft, bits<7> wuimm, string opcodestr,
+ bits<3> funct3, dag outs, dag ins, string argstr>
+ : RVInstIBase<funct3, OPC_OP_IMM_32, outs, ins, opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-28} = f;
+ let Inst{27} = aft;
+ let Inst{26-20} = wuimm;
+}
+
+class RVPUnary1F0<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<1, f, 0, wuimm, opcodestr, 0b100, (outs GPR:$rd),
+ (ins GPR:$rs1), "$rd, $rs1">;
+
+class RVPUnary0F0Rdp<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b010, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1), "$rdp, $rs1"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPUnary0F0Rs1p<bits<3> f, bits<7> wuimm, string opcodestr>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b100, (outs GPR:$rd),
+ (ins RVPGPRPairRV32:$rs1p), "$rd, $rs1p"> {
+ bits<4> rs1p;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = 0b1;
+}
+
+class RVPUnary0F0Rs1pRdp<bits<3> f, bits<7> wuimm, string opcodestr,
+ bit aft = 0b0>
+ : RVPUnaryF<0, f, 0, wuimm, opcodestr, 0b110, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p), "$rdp, $rs1p"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinaryFW<bit bfr, bits<3> f, bit aft, bits<2> w, string opcodestr,
+ bits<3> funct3, RISCVOpcode Opcode = OPC_OP_32,
+ dag outs = (outs GPR:$rd), dag ins = (ins GPR:$rs1, GPR:$rs2),
+ string argstr = "$rd, $rs1, $rs2">
+ : RVInstRBase<funct3, Opcode, outs, ins, opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-28} = f;
+ let Inst{27} = aft;
+ let Inst{26-25} = w;
+}
+
+class RVPBinary1F1W<bits<3> f, bits<2> w, string opcodestr, bits<3> funct3,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<1, f, 1, w, opcodestr, funct3, Opcode>;
+
+class RVPBinary1F0W<bits<3> f, bits<2> w, string opcodestr, bits<3> funct3,
+ RISCVOpcode Opcode = OPC_OP_32>
+ : RVPBinaryFW<1, f, 0, w, opcodestr, funct3, Opcode>;
+
+class RVPBinary0F1WRdp<bits<3> f, bits<2> w, string opcodestr,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, opcodestr, 0b010, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1, GPR:$rs2), "$rdp, $rs1, $rs2"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPBinary0F1WRs1p<bits<3> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, opcodestr, 0b100, Opcode, (outs GPR:$rd),
+ (ins RVPGPRPairRV32:$rs1p, GPR:$rs2), "$rd, $rs1p, $rs2"> {
+ bits<4> rs1p;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+}
+
+class RVPBinary0F1WRs1pRdp<bits<3> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<0, f, 1, w, opcodestr, 0b110, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, GPR:$rs2), "$rdp, $rs1p, $rs2"> {
+ bits<4> rs1p;
+ bits<4> rdp;
+
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinary1FWRs2pRs1pRdp<bits<4> f, bits<2> w, string opcodestr,
+ bit aft = 0b0, RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVInstRBase<0b110, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, RVPGPRPairRV32:$rs2p),
+ opcodestr, "$rdp, $rs1p, $rs2p"> {
+ bits<4> rs1p;
+ bits<4> rs2p;
+ bits<4> rdp;
+
+ let Inst{31} = 0b1;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+ let Inst{24-21} = rs2p;
+ let Inst{20} = aft;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+class RVPBinary1F0WRs2pRs1pRdp<bits<3> f, bits<2> w, string opcodestr,
+ bit bfr = 0b1, bit aft = 0b0,
+ RISCVOpcode Opcode = OPC_OP_IMM_32>
+ : RVPBinaryFW<1, f, 0, w, opcodestr, 0b110, Opcode, (outs RVPGPRPairRV32:$rdp),
+ (ins RVPGPRPairRV32:$rs1p, RVPGPRPairRV32:$rs2p), "$rdp, $rs1p, $rs2p"> {
+ bits<4> rs1p;
+ bits<4> rs2p;
+ bits<4> rdp;
+
+ let Inst{24-21} = rs2p;
+ let Inst{20} = bfr;
+ let Inst{19-16} = rs1p;
+ let Inst{15} = aft;
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPBinaryLongFW<bit bfr = 1, bits<4> f, bits<2> w, string opcodestr,
+ bits<3> funct3, dag outs, dag ins, string argstr>
+ : RVInstRBase<funct3, OPC_OP_32, outs, ins,
+ opcodestr, argstr> {
+ let Inst{31} = bfr;
+ let Inst{30-27} = f;
+ let Inst{26-25} = w;
+}
+
+class RVPBinary1LongFW<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
+ : RVPBinaryLongFW<1, f, w, opcodestr, funct3, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), "$rd, $rs1, $rs2">;
+
+class RVPBinary0LongFW<bits<4> f, bits<2> w, string opcodestr>
+ : RVPBinaryLongFW<0, f, w, opcodestr, 0b010, (outs RVPGPRPairRV32:$rdp),
+ (ins GPR:$rs1, RVPGPRPairRV32:$rs2), "$rdp, $rs1, $rs2"> {
+ bits<4> rdp;
+
+ let Inst{11-8} = rdp;
+ let Inst{7} = 0b1;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtP] in {
+def CLS : RVPUnary<0b01100, 0b0000011, 0b001, OPC_OP_IMM, "cls">;
+def ABS : RVPUnary<0b01100, 0b0000111, 0b001, OPC_OP_IMM, "abs">;
+} // Predicates = [HasStdExtP]
+let Predicates = [HasStdExtP, IsRV32] in
+def REV_RV32 : RVPUnary<0b01101, 0b0011111, 0b101, OPC_OP_IMM, "rev">;
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def REV16 : RVPUnary<0b01101, 0b0110000, 0b101, OPC_OP_IMM, "rev16">;
+def REV_RV64 : RVPUnary<0b01111, 0b0111111, 0b101, OPC_OP_IMM, "rev">;
+
+def CLSW : RVPUnary<0b01100, 0b0000011, 0b001, OPC_OP_IMM_32, "clsw">;
+def ABSW : RVPUnary<0b01100, 0b0000111, 0b001, OPC_OP_IMM_32, "absw">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+def PSLLI_B : RVPUnary<0b10000, 0b0001000, 0b010, OPC_OP_IMM_32, "pslli.b">;
+def PSLLI_H : RVPUnary<0b10000, 0b0010000, 0b010, OPC_OP_IMM_32, "pslli.h">;
+def PSSLAI_H : RVPUnary<0b11010, 0b0010000, 0b010, OPC_OP_IMM_32, "psslai.h">;
+} // Predicates = [HasStdExtP]
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in
+def SSLAI : RVPUnary<0b11010, 0b0100000, 0b010, OPC_OP_IMM_32, "sslai">;
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSLLI_W : RVPUnary<0b10000, 0b0100000, 0b010, OPC_OP_IMM_32, "pslli.w">;
+def PSSLAI_W : RVPUnary<0b11010, 0b0100000, 0b010, OPC_OP_IMM_32, "psslai.w">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in
+def PLI_H : RVPUnaryImm9<0b1011000, "pli.h">;
+let Predicates = [HasStdExtP, IsRV64] in
+def PLI_W : RVPUnaryImm9<0b1011001, "pli.w">;
+let Predicates = [HasStdExtP] in
+def PLI_B : RVPUnaryImm8<0b10110100, "pli.b">;
+
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def PSEXT_H_B_RV32 : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">;
+def PSABS_H_RV32 : RVPUnaryWUF<0b00, 0b00111, "psabs.h">;
+def PSABS_B_RV32 : RVPUnaryWUF<0b01, 0b00111, "psabs.b">;
+} // Predicates = [HasStdExtP, IsRV32]
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSEXT_H_B_RV64 : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">;
+def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">;
+def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">;
+def PSABS_H_RV64 : RVPUnaryWUF<0b00, 0b00111, "psabs.h">;
+def PSABS_B_RV64 : RVPUnaryWUF<0b10, 0b00111, "psabs.b">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in
+def PLUI_H : RVPUnaryImm9<0b1111000, "plui.h">;
+let Predicates = [HasStdExtP, IsRV64] in
+def PLUI_W : RVPUnaryImm9<0b1111001, "plui.w">;
+
+let Predicates = [HasStdExtP] in {
+def PSLL_HS : RVPBinary1F1W<0b000, 0b00, "psll.hs", 0b010>;
+def PSLL_BS : RVPBinary1F1W<0b000, 0b10, "psll.bs", 0b010>;
+def PADD_HS : RVPBinary1F1W<0b001, 0b00, "padd.hs", 0b010>;
+def PADD_BS : RVPBinary1F1W<0b001, 0b10, "padd.bs", 0b010>;
+def PSSHA_HS : RVPBinary1F1W<0b110, 0b00, "pssha.hs", 0b010>;
+def PSSHAR_HS : RVPBinary1F1W<0b111, 0b00, "psshar.hs", 0b010>;
+} // Predicates = [HasStdExtP]
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def SSHA : RVPBinary1F1W<0b110, 0b01, "ssha", 0b010>;
+def SSHAR : RVPBinary1F1W<0b111, 0b01, "sshar", 0b010>;
+} // Predicates = [HasStdExtP, IsRV32]
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSLL_WS : RVPBinary1F1W<0b000, 0b01, "psll.ws", 0b010>;
+def PADD_WS : RVPBinary1F1W<0b001, 0b01, "padd.ws", 0b010>;
+def PSSHA_WS : RVPBinary1F1W<0b110, 0b01, "pssha.ws", 0b010>;
+def PSSHAR_WS : RVPBinary1F1W<0b111, 0b01, "psshar.ws", 0b010>;
+def SHA : RVPBinary1F1W<0b110, 0b11, "sha", 0b010>;
+def SHAR : RVPBinary1F1W<0b111, 0b11, "shar", 0b010>;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+def PSRLI_B : RVPUnary1F0<0b000, 0b0001000, "psrli.b">;
+def PSRLI_H : RVPUnary1F0<0b000, 0b0010000, "psrli.h">;
+def PUSATI_H : RVPUnary1F0<0b010, 0b0010000, "pusati.h">;
+def PSRAI_B : RVPUnary1F0<0b100, 0b0001000, "psrai.b">;
+def PSRAI_H : RVPUnary1F0<0b100, 0b0010000, "psrai.h">;
+def PSRARI_H : RVPUnary1F0<0b101, 0b0010000, "psrari.h">;
+def PSATI_H : RVPUnary1F0<0b110, 0b0010000, "psati.h">;
+} // Predicates = [HasStdExtP]
+
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def USATI_RV32 : RVPUnary1F0<0b010, 0b0100000, "usati">;
+def SRARI : RVPUnary1F0<0b101, 0b0100000, "srari">;
+def SATI : RVPUnary1F0<0b110, 0b0100000, "sati">;
+} // Predicates = [HasStdExtP, IsRV32]
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSRLI_W : RVPUnary1F0<0b000, 0b0100000, "psrli.w">;
+def PUSATI_W : RVPUnary1F0<0b010, 0b0100000, "pusati.w">;
+def USATI_RV64 : RVPUnary1F0<0b010, 0b1000000, "usati">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+let Predicates = [HasStdExtP] in {
+def PSRL_HS : RVPBinary1F1W<0b000, 0b00, "psrl.hs", 0b100>;
+def PSRL_BS : RVPBinary1F1W<0b000, 0b10, "psrl.bs", 0b100>;
+def PREDSUM_HS : RVPBinary1F1W<0b001, 0b00, "predsum.hs", 0b100>;
+def PREDSUM_BS : RVPBinary1F1W<0b001, 0b10, "predsum.bs", 0b100>;
+def PREDSUMU_HS : RVPBinary1F1W<0b011, 0b00, "predsumu.hs", 0b100>;
+def PREDSUMU_BS : RVPBinary1F1W<0b011, 0b10, "predsumu.bs", 0b100>;
+def PSRA_HS : RVPBinary1F1W<0b100, 0b00, "psra.hs", 0b100>;
+def PSRA_BS : RVPBinary1F1W<0b100, 0b10, "psra.bs", 0b100>;
+} // Predicates = [HasStdExtP]
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSRL_WS : RVPBinary1F1W<0b000, 0b01, "psrl.ws", 0b100>;
+def PREDSUM_WS : RVPBinary1F1W<0b001, 0b01, "predsum.ws", 0b100>;
+def PREDSUMU_WS : RVPBinary1F1W<0b011, 0b01, "predsumu.ws", 0b100>;
+def PSRA_WS : RVPBinary1F1W<0b100, 0b01, "psra.ws", 0b100>;
+} // Predicates = [HasStdExtP, IsRV64]
+
+
+let Predicates = [HasStdExtP] in {
+def PADD_H : RVPBinary1LongFW<0b0000, 0b00, 0b000, "padd.h">;
+def PADD_B : RVPBinary1LongFW<0b0000, 0b10, 0b000, "padd.b">;
+def PSADD_H : RVPBinary1LongFW<0b0010, 0b00, 0b000, "psadd.h">;
+def PSADD_B : RVPBinary1LongFW<0b0010, 0b10, 0b000, "psadd.b">;
+def PAADD_H : RVPBinary1LongFW<0b0011, 0b00, 0b000, "paadd.h">;
+def PAADD_B : RVPBinary1LongFW<0b0011, 0b10, 0b000, "paadd.b">;
+
+def PSADDU_H : RVPBinary1LongFW<0b0110, 0b00, 0b000, "psaddu.h">;
+def PSADDU_B : RVPBinary1LongFW<0b0110, 0b10, 0b000, "psaddu.b">;
+def PAADDU_H : RVPBinary1LongFW<0b0111, 0b00, 0b000, "paaddu.h">;
+def PAADDU_B : RVPBinary1LongFW<0b0111, 0b10, 0b000, "paaddu.b">;
+
+def PSUB_H : RVPBinary1LongFW<0b1000, 0b00, 0b000, "psub.h">;
+def PSUB_B : RVPBinary1LongFW<0b1000, 0b10, 0b000, "psub.b">;
+def PDIF_H : RVPBinary1LongFW<0b1001, 0b00, 0b000, "pdif.h">;
+def PDIF_B : RVPBinary1LongFW<0b1001, 0b10, 0b000, "pdif.b">;
+def PSSUB_H : RVPBinary1LongFW<0b1010, 0b00, 0b000, "pssub.h">;
+def PSSUB_B : RVPBinary1LongFW<0b1010, 0b10, 0b000, "pssub.b">;
+def PASUB_H : RVPBinary1LongFW<0b1011, 0b00, 0b000, "pasub.h">;
+def PASUB_B : RVPBinary1LongFW<0b1011, 0b10, 0b000, "pasub.b">;
+
+def PDIFU_H : RVPBinary1LongFW<0b1101, 0b00, 0b000, "pdifu.h">;
+def PDIFU_B : RVPBinary1LongFW<0b1101, 0b10, 0b000, "pdifu.b">;
+def PSSUBU_H : RVPBinary1LongFW<0b1110, 0b00, 0b000, "pssubu.h">;
+def PSSUBU_B : RVPBinary1LongFW<0b1110, 0b10, 0b000, "pssubu.b">;
+def PASUBU_H : RVPBinary1LongFW<0b1111, 0b00, 0b000, "pasubu.h">;
+def PASUBU_B : RVPBinary1LongFW<0b1111, 0b10, 0b000, "pasubu.b">;
+} // Predicates = [HasStdExtP]
+
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def SADD : RVPBinary1LongFW<0b0010, 0b01, 0b000, "sadd">;
+def AADD : RVPBinary1LongFW<0b0011, 0b01, 0b000, "aadd">;
+
+def SADDU : RVPBinary1LongFW<0b0110, 0b01, 0b000, "saddu">;
+def AADDU : RVPBinary1LongFW<0b0111, 0b01, 0b000, "aaddu">;
+
+def SSUB : RVPBinary1LongFW<0b1010, 0b01, 0b000, "ssub">;
+def ASUB : RVPBinary1LongFW<0b1011, 0b01, 0b000, "asub">;
+
+def SSUBU : RVPBinary1LongFW<0b1110, 0b01, 0b000, "ssubu">;
+def ASUBU : RVPBinary1LongFW<0b1111, 0b01, 0b000, "asubu">;
+} // Predicates = [HasStdExtP, IsRV32]
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def PADD_W : RVPBinary1LongFW<0b0000, 0b01, 0b000, "padd.w">;
+def PSADD_W : RVPBinary1LongFW<0b0010, 0b01, 0b000, "psadd.w">;
+def PAADD_W : RVPBinary1LongFW<0b0011, 0b01, 0b000, "paadd.w">;
+
+def PSADDU_W : RVPBinary1LongFW<0b0110, 0b01, 0b000, "psaddu.w">;
+def PAADDU_W : RVPBinary1LongFW<0b0111, 0b01, 0b000, "paaddu.w">;
+
+def PSUB_W : RVPBinary1LongFW<0b1000, 0b01, 0b000, "psub.w">;
+def PSSUB_W : RVPBinary1LongFW<0b1010, 0b01, 0b000, "pssub.w">;
+def PASUB_W : RVPBinary1LongFW<0b1011, 0b01, 0b000, "pasub.w">;
+
+def PSSUBU_W : RVPBinary1LongFW<0b1110, 0b01, 0b000, "pssubu.w">;
+def PASUBU_W : RVPBinary1LongFW<0b1111, 0b01, 0b000, "pasubu.w">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+
+let Predicates = [HasStdExtP] in {
+def SLX : RVPBinary1LongFW<0b0001, 0b11, 0b001, "slx">;
+def PMUL_H_B01 : RVPBinary1LongFW<0b0010, 0b00, 0b001, "pmul.h.b01">;
+
+def MVM : RVPBinary1LongFW<0b0101, 0b00, 0b001, "mvm">;
+def MVMN : RVPBinary1LongFW<0b0101, 0b01, 0b001, "mvmn">;
+def MERGE : RVPBinary1LongFW<0b0101, 0b10, 0b001, "merge">;
+def SRX : RVPBinary1LongFW<0b0101, 0b11, 0b001, "srx">;
+def PMULU_H_B01 : RVPBinary1LongFW<0b0110, 0b00, 0b001, "pmulu.h.b01">;
+def PDIFSUMU_B : RVPBinary1LongFW<0b0110, 0b10, 0b001, "pdifsumu.b">;
+def PDIFSUMAU_B : RVPBinary1LongFW<0b0111, 0b10, 0b001, "pdifsumau.b">;
+} // Predicates = [HasStdExtP]
+
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def MUL_H01 : RVPBinary1LongFW<0b0010, 0b01, 0b001, "mul.h01">;
+def MACC_H01 : RVPBinary1LongFW<0b0011, 0b01, 0b001, "macc.h01">;
+
+def MULU_H01 : RVPBinary1LongFW<0b0110, 0b01, 0b001, "mulu.h01">;
+def MACCU_H01 : RVPBinary1LongFW<0b0111, 0b01, 0b001, "maccu.h01">;
+} // Predicates = [HasStdExtP, IsRV32]
+
+let Predicates = [HasStdExtP, IsRV64] in {
+def PMUL_W_H01 : RVPBinary1LongFW<0b0010, 0b01, 0b001, "pmul.w.h01">;
+def MUL_W01 : RVPBinary1LongFW<0b0010, 0b11, 0b001, "mul.w01">;
+def PMACC_W_H01 : RVPBinary1LongFW<0b0011, 0b01, 0b001, "pmacc.w.h01">;
+def MACC_W01 : RVPBinary1LongFW<0b0011, 0b11, 0b001, "macc.w01">;
+
+def PMULU_W_H01 : RVPBinary1LongFW<0b0110, 0b01, 0b001, "pmulu.w.h01">;
+def MULU_W01 : RVPBinary1LongFW<0b0110, 0b11, 0b001, "mulu.w01">;
+def PMACCU_W_H01 : RVPBinary1LongFW<0b0111, 0b01, 0b001, "pmaccu.w.h01">;
+def MACCU_W01 : RVPBinary1LongFW<0b0111, 0b11, 0b001, "maccu.w01">;
+} // Predicates = [HasStdExtP, IsRV64]
+
+
+let Predicates = [HasStdExtP] in {
+def PSH1ADD_H : RVPBinary1F0W<0b010, 0b00, "psh1add.h", 0b010>;
+def PSSH1SADD_H : RVPBinary1F0W<0b011, 0b00, "pssh1sadd.h", 0b010>;
+} // Predicates = [HasStdExtP]
+
+let DecoderNamespace = "RISCV32Only_",
+ Predicates = [HasStdExtP, IsRV32] in {
+def SSH1SADD : RVPBinary1F0W<0b010, 0b01, "ssh1sadd", 0b010>;
+} // Predicates = [HasStdExtP, IsRV32]
+let Predicates = [HasStdExtP, IsRV64] in {
+def PSH1ADD_W : RVPBinary1F0W<0b010, 0b01, "psh1add.w", 0b010>;
+def PSSH1SADD_W : RVPBinary1F0W<0b011, 0b01, "pssh1sadd.w", 0b010>;
+
+def UNZIP8P : RVPBinary1F0W<0b110, 0b00, "unzip8p", 0b010>;
----------------
topperc wrote:
Can we put the opcode string at the end to line up the columns between instructions
https://github.com/llvm/llvm-project/pull/123271
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