[llvm] [AMD][GISel] legalize `G_INSERT_SUBVECTOR` (PR #128924)

via llvm-commits llvm-commits at lists.llvm.org
Wed Feb 26 10:00:44 PST 2025


github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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``````````bash
git-clang-format --diff 3e61c1ab7f5d9666db88069d49c8916c40fae5ea 91cd376426d91d620521a1e79db31ea7ee9f1245 --extensions h,cpp -- llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp llvm/lib/CodeGen/GlobalISel/Utils.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index c88bf44c9b..b81e958ac2 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -1382,9 +1382,9 @@ public:
   }
 
   MachineInstrBuilder buildInsertVectorElementConstant(const DstOp &Res,
-                                                        const SrcOp &Val,
-                                                        const SrcOp &Elt,
-                                                        const int Idx) {
+                                                       const SrcOp &Val,
+                                                       const SrcOp &Elt,
+                                                       const int Idx) {
     auto TLI = getMF().getSubtarget().getTargetLowering();
     unsigned VecIdxWidth = TLI->getVectorIdxTy(getDataLayout()).getSizeInBits();
     return buildInsertVectorElement(
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 107bb4f63f..5ace75f6c4 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -126,7 +126,7 @@ LegalizerHelper::legalizeInstrStep(MachineInstr &MI,
     return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize;
   if (isa<GInsertSubvector>(MI))
     return LI.legalizeCustom(*this, MI, LocObserver) ? Legalized
-                                                 : UnableToLegalize;
+                                                     : UnableToLegalize;
   auto Step = LI.getAction(MI, MRI);
   switch (Step.Action) {
   case Legal:
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 92266e0d0e..a754419ec9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2869,7 +2869,8 @@ bool AMDGPULegalizerInfo::legalizeInsertSubVector(MachineInstr &MI,
       } else {
         Elt = B.buildExtractVectorElementConstant(S32, InsB, I);
       }
-      VecB = B.buildInsertVectorElementConstant(NewVecVT, VecB, Elt, IdxVal / 2 + I);
+      VecB = B.buildInsertVectorElementConstant(NewVecVT, VecB, Elt,
+                                                IdxVal / 2 + I);
     }
     auto R = B.buildBitcast(VecVT, VecB);
     MI.eraseFromParent();
@@ -2878,7 +2879,8 @@ bool AMDGPULegalizerInfo::legalizeInsertSubVector(MachineInstr &MI,
 
   for (unsigned I = 0; I != InsNumElts; ++I) {
     auto Elt = B.buildExtractVectorElementConstant(EltVT, Ins, I);
-    Vec = B.buildInsertVectorElementConstant(VecVT, Vec, Elt, IdxVal + I).getReg(0);
+    Vec = B.buildInsertVectorElementConstant(VecVT, Vec, Elt, IdxVal + I)
+              .getReg(0);
   }
 
   MI.eraseFromParent();

``````````

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https://github.com/llvm/llvm-project/pull/128924


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