[llvm] [TargetInstrInfo] Add target hook for InstrSchedModel latency. [NFCI] (PR #128925)

[via llvm-commits]

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git-clang-format --diff 98542a3d6d087e1baf6c90d134140e2ed858f823 fe6782da986b184d334b222a2adfefa4aa4b4bb4 --extensions cpp,h -- llvm/include/llvm/CodeGen/TargetInstrInfo.h llvm/include/llvm/CodeGen/TargetSchedule.h llvm/lib/CodeGen/TargetInstrInfo.cpp llvm/lib/CodeGen/TargetSchedule.cpp
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View the diff from clang-format here.
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diff --git a/llvm/include/llvm/CodeGen/TargetSchedule.h b/llvm/include/llvm/CodeGen/TargetSchedule.h
index 3c5c3aa8b5..3b52c8f47d 100644
--- a/llvm/include/llvm/CodeGen/TargetSchedule.h
+++ b/llvm/include/llvm/CodeGen/TargetSchedule.h
@@ -189,7 +189,6 @@ public:
   unsigned computeInstrLatency(unsigned Opcode) const;
   unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
-
   /// Output dependency latency of a pair of defs of the same register.
   ///
   /// This is typically one cycle.

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https://github.com/llvm/llvm-project/pull/128925