[llvm] [RISCV] Order the implicit defs on MC vset(i)vl(i) instructions the same as the pseudo version. (PR #129104)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

<details>
<summary>Changes</summary>

This doesn't really matter, but its good to be consistent. There is code that depends on the pseudo order so it was easier to change the MC order.

---
Full diff: https://github.com/llvm/llvm-project/pull/129104.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrFormatsV.td (+3-3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index 6f27c98dd6183..3235b601d4774 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -68,7 +68,7 @@ class RVInstSetiVLi<dag outs, dag ins, string opcodestr, string argstr>
   let Inst{11-7} = rd;
   let Inst{6-0} = OPC_OP_V.Value;
 
-  let Defs = [VTYPE, VL];
+  let Defs = [VL, VTYPE];
 }
 
 class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
@@ -84,7 +84,7 @@ class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
   let Inst{11-7} = rd;
   let Inst{6-0} = OPC_OP_V.Value;
 
-  let Defs = [VTYPE, VL];
+  let Defs = [VL, VTYPE];
 }
 
 class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
@@ -101,7 +101,7 @@ class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
   let Inst{11-7} = rd;
   let Inst{6-0} = OPC_OP_V.Value;
 
-  let Defs = [VTYPE, VL];
+  let Defs = [VL, VTYPE];
 }
 
 class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,

``````````

</details>


https://github.com/llvm/llvm-project/pull/129104