[llvm] [RISCV] Use addiw for or_is_add when or input is sign extended. (PR #128635)

[Philip Reames via llvm-commits]

https://github.com/preames approved this pull request.

LGTM.

This feels a bit like fixing a symptom instead of the true cause.  A worthwhile thing to do, but should we go further than this and extend the reasoning in the sext.w removal pas too?

https://github.com/llvm/llvm-project/pull/128635