[llvm] [X86][DAGCombiner] Skip x87 fp80 values in `combineFMulOrFDivWithIntPow2` (PR #128618)
Yingwei Zheng via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 24 23:37:06 PST 2025
https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/128618
>From 53eea161449cad0af7accce89b5bdbd732651fac Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 25 Feb 2025 10:26:04 +0800
Subject: [PATCH 1/4] [X86][DAGCombiner] Add pre-commit tests. NFC.
---
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index e513b666ebf83..bda6df5707801 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -1688,3 +1688,43 @@ define float @fdiv_pow_shl_cnt32_okay(i32 %cnt) nounwind {
%mul = fdiv float 0x3a20000000000000, %conv
ret float %mul
}
+
+define x86_fp80 @pr128528(i1 %cond) {
+; CHECK-SSE-LABEL: pr128528:
+; CHECK-SSE: # %bb.0:
+; CHECK-SSE-NEXT: xorl %eax, %eax
+; CHECK-SSE-NEXT: testb $1, %dil
+; CHECK-SSE-NEXT: setne %al
+; CHECK-SSE-NEXT: movq %rax, %rcx
+; CHECK-SSE-NEXT: shlq $63, %rcx
+; CHECK-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
+; CHECK-SSE-NEXT: fstpt -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: addq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
+; CHECK-SSE-NEXT: adcq %rax, %rcx
+; CHECK-SSE-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: fldt -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: retq
+;
+; CHECK-AVX-LABEL: pr128528:
+; CHECK-AVX: # %bb.0:
+; CHECK-AVX-NEXT: xorl %eax, %eax
+; CHECK-AVX-NEXT: testb $1, %dil
+; CHECK-AVX-NEXT: setne %al
+; CHECK-AVX-NEXT: movq %rax, %rcx
+; CHECK-AVX-NEXT: shlq $63, %rcx
+; CHECK-AVX-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
+; CHECK-AVX-NEXT: fstpt -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: addq -{{[0-9]+}}(%rsp), %rcx
+; CHECK-AVX-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
+; CHECK-AVX-NEXT: adcq %rax, %rcx
+; CHECK-AVX-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: fldt -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: retq
+ %sub9 = select i1 %cond, i32 8, i32 1
+ %conv = uitofp i32 %sub9 to x86_fp80
+ %mul = fmul x86_fp80 %conv, 0xK4007D055555555555800
+ ret x86_fp80 %mul
+}
>From 2ea93f932c84f249ba3bc1d281c78612a19430ff Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 25 Feb 2025 10:35:30 +0800
Subject: [PATCH 2/4] [X86][DAGCombiner] Skip x87 f80 values in
`combineFMulOrFDivWithIntPow2`
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 +++--
.../X86/fold-int-pow2-with-fmul-or-fdiv.ll | 36 +++++++------------
2 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a83be13ebff2b..7347923c7d33d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17271,6 +17271,10 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
// prefer it.
SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) {
EVT VT = N->getValueType(0);
+ if (!Type::getFloatingPointTy(*DAG.getContext(), VT.getFltSemantics())
+ ->isIEEELikeFPTy())
+ return SDValue();
+
SDValue ConstOp, Pow2Op;
std::optional<int> Mantissa;
@@ -17297,8 +17301,8 @@ SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) {
const APFloat &APF = CFP->getValueAPF();
- // Make sure we have normal/ieee constant.
- if (!APF.isNormal() || !APF.isIEEE())
+ // Make sure we have normal constant.
+ if (!APF.isNormal())
return false;
// Make sure the floats exponent is within the bounds that this transform
diff --git a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
index bda6df5707801..67c9e7cc22236 100644
--- a/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ b/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -1692,36 +1692,24 @@ define float @fdiv_pow_shl_cnt32_okay(i32 %cnt) nounwind {
define x86_fp80 @pr128528(i1 %cond) {
; CHECK-SSE-LABEL: pr128528:
; CHECK-SSE: # %bb.0:
-; CHECK-SSE-NEXT: xorl %eax, %eax
; CHECK-SSE-NEXT: testb $1, %dil
-; CHECK-SSE-NEXT: setne %al
-; CHECK-SSE-NEXT: movq %rax, %rcx
-; CHECK-SSE-NEXT: shlq $63, %rcx
-; CHECK-SSE-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
-; CHECK-SSE-NEXT: fstpt -{{[0-9]+}}(%rsp)
-; CHECK-SSE-NEXT: addq -{{[0-9]+}}(%rsp), %rcx
-; CHECK-SSE-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; CHECK-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
-; CHECK-SSE-NEXT: adcq %rax, %rcx
-; CHECK-SSE-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
-; CHECK-SSE-NEXT: fldt -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: movl $8, %eax
+; CHECK-SSE-NEXT: movl $1, %ecx
+; CHECK-SSE-NEXT: cmovnel %eax, %ecx
+; CHECK-SSE-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: fildl -{{[0-9]+}}(%rsp)
+; CHECK-SSE-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; CHECK-SSE-NEXT: retq
;
; CHECK-AVX-LABEL: pr128528:
; CHECK-AVX: # %bb.0:
-; CHECK-AVX-NEXT: xorl %eax, %eax
; CHECK-AVX-NEXT: testb $1, %dil
-; CHECK-AVX-NEXT: setne %al
-; CHECK-AVX-NEXT: movq %rax, %rcx
-; CHECK-AVX-NEXT: shlq $63, %rcx
-; CHECK-AVX-NEXT: fldl {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
-; CHECK-AVX-NEXT: fstpt -{{[0-9]+}}(%rsp)
-; CHECK-AVX-NEXT: addq -{{[0-9]+}}(%rsp), %rcx
-; CHECK-AVX-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
-; CHECK-AVX-NEXT: movl -{{[0-9]+}}(%rsp), %ecx
-; CHECK-AVX-NEXT: adcq %rax, %rcx
-; CHECK-AVX-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
-; CHECK-AVX-NEXT: fldt -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: movl $8, %eax
+; CHECK-AVX-NEXT: movl $1, %ecx
+; CHECK-AVX-NEXT: cmovnel %eax, %ecx
+; CHECK-AVX-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: fildl -{{[0-9]+}}(%rsp)
+; CHECK-AVX-NEXT: fmull {{\.?LCPI[0-9]+_[0-9]+}}(%rip)
; CHECK-AVX-NEXT: retq
%sub9 = select i1 %cond, i32 8, i32 1
%conv = uitofp i32 %sub9 to x86_fp80
>From 31b19aac0f3348efbe16a0cfd96e9f8fd87e4baf Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 25 Feb 2025 11:54:16 +0800
Subject: [PATCH 3/4] [DAGCombiner] Do not use IR types
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7347923c7d33d..5cfacdb8bbb96 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17271,8 +17271,9 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
// prefer it.
SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) {
EVT VT = N->getValueType(0);
- if (!Type::getFloatingPointTy(*DAG.getContext(), VT.getFltSemantics())
- ->isIEEELikeFPTy())
+ const fltSemantics &Sem = VT.getFltSemantics();
+ if (&Sem == &APFloat::x87DoubleExtended() ||
+ &Sem == &APFloat::PPCDoubleDouble())
return SDValue();
SDValue ConstOp, Pow2Op;
>From 392249f87e57f8851ff5283e6fd0d2291028e6a9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Tue, 25 Feb 2025 15:36:40 +0800
Subject: [PATCH 4/4] [ADT] Add a helper "APFloat::isIEEELikeFP"
---
llvm/include/llvm/ADT/APFloat.h | 1 +
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +---
llvm/lib/Support/APFloat.cpp | 5 +++++
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/ADT/APFloat.h b/llvm/include/llvm/ADT/APFloat.h
index 9792749230cbf..3bff205e7aa9e 100644
--- a/llvm/include/llvm/ADT/APFloat.h
+++ b/llvm/include/llvm/ADT/APFloat.h
@@ -353,6 +353,7 @@ struct APFloatBase {
static bool semanticsHasSignedRepr(const fltSemantics &);
static bool semanticsHasInf(const fltSemantics &);
static bool semanticsHasNaN(const fltSemantics &);
+ static bool isIEEELikeFP(const fltSemantics &);
// Returns true if any number described by \p Src can be precisely represented
// by a normal (not subnormal) value in \p Dst.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5cfacdb8bbb96..6746a5da4d633 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17271,9 +17271,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
// prefer it.
SDValue DAGCombiner::combineFMulOrFDivWithIntPow2(SDNode *N) {
EVT VT = N->getValueType(0);
- const fltSemantics &Sem = VT.getFltSemantics();
- if (&Sem == &APFloat::x87DoubleExtended() ||
- &Sem == &APFloat::PPCDoubleDouble())
+ if (!APFloat::isIEEELikeFP(VT.getFltSemantics()))
return SDValue();
SDValue ConstOp, Pow2Op;
diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp
index b0d92ae37fe8f..cbee7f48b8773 100644
--- a/llvm/lib/Support/APFloat.cpp
+++ b/llvm/lib/Support/APFloat.cpp
@@ -353,6 +353,11 @@ bool APFloatBase::semanticsHasNaN(const fltSemantics &semantics) {
return semantics.nonFiniteBehavior != fltNonfiniteBehavior::FiniteOnly;
}
+bool APFloatBase::isIEEELikeFP(const fltSemantics &semantics) {
+ // Keep in sync with Type::isIEEELikeFPTy
+ return SemanticsToEnum(semantics) <= S_IEEEquad;
+}
+
bool APFloatBase::isRepresentableAsNormalIn(const fltSemantics &Src,
const fltSemantics &Dst) {
// Exponent range must be larger.
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