[llvm] [RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (PR #129296)

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git-clang-format --diff 248be98418225fd409bc3ffb1834573c7890085e 727770a9e5f902f42682e843b75c6105a9277e54 --extensions cpp -- llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp b/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
index d82b54b70d..35a84c2f3a 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
@@ -14,7 +14,7 @@
 // 1. When tracking register pressure, we don't track physical registers.
 // 2. We have a RegisterClass for mask register (which is `VMV0`), but we don't
 //    use it by the time we reach scheduling. Instead, we use physical
-//    register V0 directly and insert a `$v0 = COPY ...` before the use. 
+//    register V0 directly and insert a `$v0 = COPY ...` before the use.
 // 3. For mask producers, we are using VR RegisterClass (we can allocate V0-V31
 //    to it). So if V0 is not available, there are still 31 available registers
 //    out there.

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https://github.com/llvm/llvm-project/pull/129296