[llvm] [AMDGPU][True16][CodeGen] 16bit spill support in true16 mode (PR #128060)

[Brox Chen via llvm-commits]

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@@ -2387,8 +2390,14 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
              MFI->getStackPtrOffsetReg());
 
-      unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR
-                                            : AMDGPU::BUFFER_STORE_DWORD_OFFSET;
+      unsigned Opc;
+      if (MI->getOpcode() == AMDGPU::SI_SPILL_V16_SAVE) {
+        Opc = AMDGPU::SCRATCH_STORE_SHORT_SADDR_t16;
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broxigarchen wrote:

I am not sure about this part. Might need some input from @Sisyph when he is back from vacation.

Added an assert first

https://github.com/llvm/llvm-project/pull/128060