[llvm] 2c1df22 - RegAllocFast: Fix 8634635d689c5a7adfb19cde4a313d7c02e95194 to not trip assertions

[Benjamin Kramer via llvm-commits]

Author: Benjamin Kramer
Date: 2025-02-26T15:37:46+01:00
New Revision: 2c1df2206189be8550a0e36a39cc185e9e3e0051

URL: https://github.com/llvm/llvm-project/commit/2c1df2206189be8550a0e36a39cc185e9e3e0051
DIFF: https://github.com/llvm/llvm-project/commit/2c1df2206189be8550a0e36a39cc185e9e3e0051.diff

LOG: RegAllocFast: Fix 8634635d689c5a7adfb19cde4a313d7c02e95194 to not trip assertions

Added: 
    

Modified: 
    llvm/lib/CodeGen/RegAllocFast.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index 3627bbb905176..d0055667770d2 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -982,9 +982,9 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) {
   if (!shouldAllocateRegister(VirtReg))
     return;
 
-  MO.setIsRenamable();
   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
   MCPhysReg PhysReg;
+  bool IsRenamable = true;
   if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
     PhysReg = LRI->PhysReg;
   } else {
@@ -998,7 +998,7 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) {
       // basic.
       PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
       LRI->Error = true;
-      MO.setIsRenamable(false);
+      IsRenamable = false;
     } else
       PhysReg = AllocationOrder.front();
   }
@@ -1009,6 +1009,7 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand &MO) {
     MO.setSubReg(0);
   }
   MO.setReg(PhysReg);
+  MO.setIsRenamable(IsRenamable);
 }
 
 /// Variation of defineVirtReg() with special handling for livethrough regs