[llvm] [LoongArch] Pre-commit tests for vector sext & zext (PR #128835)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 25 23:06:10 PST 2025
https://github.com/tangaac created https://github.com/llvm/llvm-project/pull/128835
None
>From f89edb412c929569d044a21552ba604e5c304ee0 Mon Sep 17 00:00:00 2001
From: tangaac <tangyan01 at loongson.cn>
Date: Wed, 26 Feb 2025 14:58:53 +0800
Subject: [PATCH] pre-commit tests for vector sext & zext
---
llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll | 394 ++++++++++++++++++++
llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll | 384 +++++++++++++++++++
2 files changed, 778 insertions(+)
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
create mode 100644 llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
new file mode 100644
index 0000000000000..ea9da6aa60c4a
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
@@ -0,0 +1,394 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
+
+
+define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i8_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.b $a2, $a0, 0
+; CHECK-NEXT: ld.b $a0, $a0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i8>, ptr %ptr
+ %B = sext <2 x i8> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i8_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.b $a2, $a0, 0
+; CHECK-NEXT: ld.b $a3, $a0, 1
+; CHECK-NEXT: ld.b $a4, $a0, 2
+; CHECK-NEXT: ld.b $a0, $a0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = sext <4 x i8> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i8_to_8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.b $a2, $a0, 0
+; CHECK-NEXT: ld.b $a3, $a0, 1
+; CHECK-NEXT: ld.b $a4, $a0, 2
+; CHECK-NEXT: ld.b $a5, $a0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 3
+; CHECK-NEXT: ld.b $a2, $a0, 4
+; CHECK-NEXT: ld.b $a3, $a0, 5
+; CHECK-NEXT: ld.b $a4, $a0, 6
+; CHECK-NEXT: ld.b $a0, $a0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 5
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = sext <8 x i8> %A to <8 x i16>
+ store <8 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i16_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.h $a2, $a0, 0
+; CHECK-NEXT: ld.h $a0, $a0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i16>, ptr %ptr
+ %B = sext <2 x i16> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i16_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.h $a2, $a0, 0
+; CHECK-NEXT: ld.h $a3, $a0, 2
+; CHECK-NEXT: ld.h $a4, $a0, 4
+; CHECK-NEXT: ld.h $a0, $a0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = sext <4 x i16> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_2i32_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.w $a2, $a0, 0
+; CHECK-NEXT: ld.w $a0, $a0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i32>, ptr %ptr
+ %B = sext <2 x i32> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7
+; CHECK-NEXT: vslli.h $vr1, $vr1, 8
+; CHECK-NEXT: vsrai.h $vr1, $vr1, 8
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.h $vr2, $a0, 7
+; CHECK-NEXT: vslli.h $vr0, $vr2, 8
+; CHECK-NEXT: vsrai.h $vr0, $vr0, 8
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i16>
+ store <16 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; CHECK-NEXT: vslli.w $vr1, $vr1, 24
+; CHECK-NEXT: vsrai.w $vr1, $vr1, 24
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: vslli.w $vr2, $vr2, 24
+; CHECK-NEXT: vsrai.w $vr2, $vr2, 24
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 3
+; CHECK-NEXT: vslli.w $vr3, $vr3, 24
+; CHECK-NEXT: vsrai.w $vr3, $vr3, 24
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 3
+; CHECK-NEXT: vslli.w $vr0, $vr4, 24
+; CHECK-NEXT: vsrai.w $vr0, $vr0, 24
+; CHECK-NEXT: vst $vr0, $a1, 48
+; CHECK-NEXT: vst $vr3, $a1, 32
+; CHECK-NEXT: vst $vr2, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i32>
+ store <16 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_16i8_to_16i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_16i8_to_16i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: vslli.d $vr1, $vr1, 56
+; CHECK-NEXT: vsrai.d $vr1, $vr1, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; CHECK-NEXT: vslli.d $vr2, $vr2, 56
+; CHECK-NEXT: vsrai.d $vr2, $vr2, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; CHECK-NEXT: vslli.d $vr3, $vr3, 56
+; CHECK-NEXT: vsrai.d $vr3, $vr3, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
+; CHECK-NEXT: vslli.d $vr4, $vr4, 56
+; CHECK-NEXT: vsrai.d $vr4, $vr4, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 1
+; CHECK-NEXT: vslli.d $vr5, $vr5, 56
+; CHECK-NEXT: vsrai.d $vr5, $vr5, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 1
+; CHECK-NEXT: vslli.d $vr6, $vr6, 56
+; CHECK-NEXT: vsrai.d $vr6, $vr6, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 1
+; CHECK-NEXT: vslli.d $vr7, $vr7, 56
+; CHECK-NEXT: vsrai.d $vr7, $vr7, 56
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 1
+; CHECK-NEXT: vslli.d $vr0, $vr8, 56
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
+; CHECK-NEXT: vst $vr0, $a1, 112
+; CHECK-NEXT: vst $vr7, $a1, 96
+; CHECK-NEXT: vst $vr6, $a1, 80
+; CHECK-NEXT: vst $vr5, $a1, 64
+; CHECK-NEXT: vst $vr4, $a1, 48
+; CHECK-NEXT: vst $vr3, $a1, 32
+; CHECK-NEXT: vst $vr2, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = sext <16 x i8> %A to <16 x i64>
+ store <16 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i16_to_8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; CHECK-NEXT: vslli.w $vr1, $vr1, 16
+; CHECK-NEXT: vsrai.w $vr1, $vr1, 16
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr2, $a0, 3
+; CHECK-NEXT: vslli.w $vr0, $vr2, 16
+; CHECK-NEXT: vsrai.w $vr0, $vr0, 16
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_8i16_to_8i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_8i16_to_8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: vslli.d $vr1, $vr1, 48
+; CHECK-NEXT: vsrai.d $vr1, $vr1, 48
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; CHECK-NEXT: vslli.d $vr2, $vr2, 48
+; CHECK-NEXT: vsrai.d $vr2, $vr2, 48
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; CHECK-NEXT: vslli.d $vr3, $vr3, 48
+; CHECK-NEXT: vsrai.d $vr3, $vr3, 48
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
+; CHECK-NEXT: vslli.d $vr0, $vr4, 48
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
+; CHECK-NEXT: vst $vr0, $a1, 48
+; CHECK-NEXT: vst $vr3, $a1, 32
+; CHECK-NEXT: vst $vr2, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = sext <8 x i16> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_sext_4i32_to_4i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_sext_4i32_to_4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: vslli.d $vr1, $vr1, 32
+; CHECK-NEXT: vsrai.d $vr1, $vr1, 32
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr2, $a0, 1
+; CHECK-NEXT: vslli.d $vr0, $vr2, 32
+; CHECK-NEXT: vsrai.d $vr0, $vr0, 32
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i32>, ptr %ptr
+ %B = sext <4 x i32> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
+
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
new file mode 100644
index 0000000000000..43cf68c880ff3
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
@@ -0,0 +1,384 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
+
+
+define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_2i8_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.bu $a2, $a0, 0
+; CHECK-NEXT: ld.bu $a0, $a0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i8>, ptr %ptr
+ %B = zext <2 x i8> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_4i8_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.bu $a2, $a0, 0
+; CHECK-NEXT: ld.bu $a3, $a0, 1
+; CHECK-NEXT: ld.bu $a4, $a0, 2
+; CHECK-NEXT: ld.bu $a0, $a0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i8>, ptr %ptr
+ %B = zext <4 x i8> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_8i8_to_8i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.bu $a2, $a0, 0
+; CHECK-NEXT: ld.bu $a3, $a0, 1
+; CHECK-NEXT: ld.bu $a4, $a0, 2
+; CHECK-NEXT: ld.bu $a5, $a0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a5, 3
+; CHECK-NEXT: ld.bu $a2, $a0, 4
+; CHECK-NEXT: ld.bu $a3, $a0, 5
+; CHECK-NEXT: ld.bu $a4, $a0, 6
+; CHECK-NEXT: ld.bu $a0, $a0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a2, 4
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a3, 5
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a4, 6
+; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 7
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i8>, ptr %ptr
+ %B = zext <8 x i8> %A to <8 x i16>
+ store <8 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_2i16_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.hu $a2, $a0, 0
+; CHECK-NEXT: ld.hu $a0, $a0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i16>, ptr %ptr
+ %B = zext <2 x i16> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_4i16_to_4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.hu $a2, $a0, 0
+; CHECK-NEXT: ld.hu $a3, $a0, 2
+; CHECK-NEXT: ld.hu $a4, $a0, 4
+; CHECK-NEXT: ld.hu $a0, $a0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a4, 2
+; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i16>, ptr %ptr
+ %B = zext <4 x i16> %A to <4 x i32>
+ store <4 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_2i32_to_2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ld.wu $a2, $a0, 0
+; CHECK-NEXT: ld.wu $a0, $a0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 0
+; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; CHECK-NEXT: vst $vr0, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <2 x i32>, ptr %ptr
+ %B = zext <2 x i32> %A to <2 x i64>
+ store <2 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i16(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i16:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.h $vr1, $a0, 7
+; CHECK-NEXT: vrepli.h $vr2, 255
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 3
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 4
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 5
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 6
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.h $vr3, $a0, 7
+; CHECK-NEXT: vand.v $vr0, $vr3, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i16>
+ store <16 x i16> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; CHECK-NEXT: vrepli.w $vr2, 255
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 3
+; CHECK-NEXT: vand.v $vr3, $vr3, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.w $vr4, $a0, 3
+; CHECK-NEXT: vand.v $vr4, $vr4, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.w $vr5, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.w $vr5, $a0, 1
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.w $vr5, $a0, 2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.w $vr5, $a0, 3
+; CHECK-NEXT: vand.v $vr0, $vr5, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 48
+; CHECK-NEXT: vst $vr4, $a1, 32
+; CHECK-NEXT: vst $vr3, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i32>
+ store <16 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_16i8_to_16i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_16i8_to_16i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: vrepli.d $vr2, 255
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; CHECK-NEXT: vand.v $vr3, $vr3, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
+; CHECK-NEXT: vand.v $vr4, $vr4, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 1
+; CHECK-NEXT: vand.v $vr5, $vr5, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 8
+; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 9
+; CHECK-NEXT: vinsgr2vr.d $vr6, $a0, 1
+; CHECK-NEXT: vand.v $vr6, $vr6, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 10
+; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 11
+; CHECK-NEXT: vinsgr2vr.d $vr7, $a0, 1
+; CHECK-NEXT: vand.v $vr7, $vr7, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 12
+; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 13
+; CHECK-NEXT: vinsgr2vr.d $vr8, $a0, 1
+; CHECK-NEXT: vand.v $vr8, $vr8, $vr2
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 14
+; CHECK-NEXT: vinsgr2vr.d $vr9, $a0, 0
+; CHECK-NEXT: vpickve2gr.b $a0, $vr0, 15
+; CHECK-NEXT: vinsgr2vr.d $vr9, $a0, 1
+; CHECK-NEXT: vand.v $vr0, $vr9, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 112
+; CHECK-NEXT: vst $vr8, $a1, 96
+; CHECK-NEXT: vst $vr7, $a1, 80
+; CHECK-NEXT: vst $vr6, $a1, 64
+; CHECK-NEXT: vst $vr5, $a1, 48
+; CHECK-NEXT: vst $vr4, $a1, 32
+; CHECK-NEXT: vst $vr3, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <16 x i8>, ptr %ptr
+ %B = zext <16 x i8> %A to <16 x i64>
+ store <16 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i16_to_8i32(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_8i16_to_8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.w $vr1, $a0, 3
+; CHECK-NEXT: lu12i.w $a0, 15
+; CHECK-NEXT: ori $a0, $a0, 4095
+; CHECK-NEXT: vreplgr2vr.w $vr2, $a0
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 1
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.w $vr3, $a0, 3
+; CHECK-NEXT: vand.v $vr0, $vr3, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = zext <8 x i16> %A to <8 x i32>
+ store <8 x i32> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_8i16_to_8i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_8i16_to_8i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: lu12i.w $a0, 15
+; CHECK-NEXT: ori $a0, $a0, 4095
+; CHECK-NEXT: vreplgr2vr.d $vr2, $a0
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; CHECK-NEXT: vand.v $vr3, $vr3, $vr2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 4
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 5
+; CHECK-NEXT: vinsgr2vr.d $vr4, $a0, 1
+; CHECK-NEXT: vand.v $vr4, $vr4, $vr2
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 6
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 0
+; CHECK-NEXT: vpickve2gr.h $a0, $vr0, 7
+; CHECK-NEXT: vinsgr2vr.d $vr5, $a0, 1
+; CHECK-NEXT: vand.v $vr0, $vr5, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 48
+; CHECK-NEXT: vst $vr4, $a1, 32
+; CHECK-NEXT: vst $vr3, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <8 x i16>, ptr %ptr
+ %B = zext <8 x i16> %A to <8 x i64>
+ store <8 x i64> %B, ptr %dst
+ ret void
+}
+
+define void @load_zext_4i32_to_4i64(ptr %ptr, ptr %dst) {
+; CHECK-LABEL: load_zext_4i32_to_4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 0
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
+; CHECK-NEXT: vinsgr2vr.d $vr1, $a0, 1
+; CHECK-NEXT: addi.w $a0, $zero, -1
+; CHECK-NEXT: lu32i.d $a0, 0
+; CHECK-NEXT: vreplgr2vr.d $vr2, $a0
+; CHECK-NEXT: vand.v $vr1, $vr1, $vr2
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 2
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 0
+; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
+; CHECK-NEXT: vinsgr2vr.d $vr3, $a0, 1
+; CHECK-NEXT: vand.v $vr0, $vr3, $vr2
+; CHECK-NEXT: vst $vr0, $a1, 16
+; CHECK-NEXT: vst $vr1, $a1, 0
+; CHECK-NEXT: ret
+entry:
+ %A = load <4 x i32>, ptr %ptr
+ %B = zext <4 x i32> %A to <4 x i64>
+ store <4 x i64> %B, ptr %dst
+ ret void
+}
+
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