[llvm] [AMDGPU] Account for existing SDWA selections (PR #123221)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,796 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -simplify-mir -run-pass=si-peephole-sdwa -o - %s | FileCheck %s
+
+# Test the combination of SDWA selections in si-peephole-sdwa. In each
+# example, the SDWA source selection specified on the last instruction
+# must be combined with the source selection that the pass determines
+# for this operand, i.e. the second instruction.  In the cases where
+# this is not possible, no conversion should occur, i.e. the last
+# instruction in the output mir should still use the second
+# instruction with the same source selection.
+
+---
+name: op_select_byte0_instr_select_dword
+body:             |
+
+  bb.0:
+    ; CHECK-LABEL: name: op_select_byte0_instr_select_dword
+    ; CHECK: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, $vgpr0, 0, $vgpr0, 0, 1, 0, 5, 0, implicit $exec
+    ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 255, [[V_LSHRREV_B32_sdwa]], implicit $exec
+    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[V_LSHRREV_B32_sdwa]], 0, [[V_LSHRREV_B32_sdwa]], 0, 1, 0, 0, 0, implicit $exec
+    ; CHECK-NEXT: S_ENDPGM 0
+    %3:vgpr_32 = V_LSHRREV_B32_sdwa 0, $vgpr0, 0, $vgpr0, 0, 1, 0, 5, 0, implicit $exec
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arsenm wrote:

Why are these using physical registers? This should never appear here. Physical register uses should only occur in edge case tests involving physical registers, they shouldn't be used in a normal case

https://github.com/llvm/llvm-project/pull/123221