[llvm] True16 Add OpSel when optimizing exec mask (PR #128928)
Brox Chen via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 27 11:50:46 PST 2025
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/128928
>From bc8fd8f6e3217e1d54a2e955a3f9893700faf5eb Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Wed, 26 Feb 2025 13:13:05 -0500
Subject: [PATCH] True16 Add OpSel when optimizing exec mask
True16 VOPCX have the opsel argument. Add it when we create these
instructions in SIOptimizeExecMasking.
---
.../Target/AMDGPU/SIOptimizeExecMasking.cpp | 2 +
llvm/test/CodeGen/AMDGPU/true16-saveexec.mir | 64 +++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 920c3e11e4718..745e4086bc7fe 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -632,6 +632,8 @@ bool SIOptimizeExecMasking::optimizeVCMPSaveExecSequence(
TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::clamp);
+ TryAddImmediateValueFromNamedOperand(AMDGPU::OpName::op_sel);
+
// The kill flags may no longer be correct.
if (Src0->isReg())
MRI->clearKillFlags(Src0->getReg());
diff --git a/llvm/test/CodeGen/AMDGPU/true16-saveexec.mir b/llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
new file mode 100644
index 0000000000000..07259a1d031f3
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/true16-saveexec.mir
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+# RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -run-pass=si-optimize-exec-masking -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: int
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: int
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr20
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
+ ; CHECK-NEXT: V_CMPX_LT_I16_t16_nosdst_e64 0, 15, 0, $vgpr20_lo16, 0, implicit-def $exec, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr0_sgpr1 = S_XOR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def dead $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.1:
+ liveins: $vgpr20
+ $vcc = V_CMP_LT_I16_t16_e64 0, 15, 0, $vgpr20_lo16, 0, implicit $exec
+ renamable $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+ renamable $sgpr2_sgpr3 = S_AND_B64 renamable $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+ renamable $sgpr0_sgpr1 = S_XOR_B64 renamable $sgpr2_sgpr3, killed renamable $sgpr0_sgpr1, implicit-def dead $scc
+ $exec = S_MOV_B64_term killed renamable $sgpr2_sgpr3
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ S_ENDPGM 0
+...
+
+---
+name: float
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: float
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $vgpr20
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $sgpr0_sgpr1 = S_MOV_B64 $exec
+ ; CHECK-NEXT: V_CMPX_LT_F16_t16_nosdst_e64 0, 15, 0, $vgpr20_lo16, 1, 0, implicit-def $exec, implicit $mode, implicit $exec
+ ; CHECK-NEXT: renamable $sgpr0_sgpr1 = S_XOR_B64 $exec, killed renamable $sgpr0_sgpr1, implicit-def dead $scc
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.1:
+ liveins: $vgpr20
+ $vcc = V_CMP_LT_F16_t16_e64 0, 15, 0, $vgpr20_lo16, 1, 0, implicit $exec, implicit $mode
+ renamable $sgpr0_sgpr1 = COPY $exec, implicit-def $exec
+ renamable $sgpr2_sgpr3 = S_AND_B64 renamable $sgpr0_sgpr1, killed $vcc, implicit-def dead $scc
+ renamable $sgpr0_sgpr1 = S_XOR_B64 renamable $sgpr2_sgpr3, killed renamable $sgpr0_sgpr1, implicit-def dead $scc
+ $exec = S_MOV_B64_term killed renamable $sgpr2_sgpr3
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.2:
+ S_ENDPGM 0
+...
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