The Week Of Monday 21 April 2025 Archives by thread
Starting: Mon Apr 21 00:01:49 PDT 2025
Ending: Tue Apr 22 22:38:42 PDT 2025
Messages: 2077
- [libcxx] [llvm] Add C++23 stacktrace (P0881R7) (PR #136528)
Hristo Hristov via llvm-commits
- [llvm] b6820c3 - [MachinePipeliner] Remove UB from tests (NFC) (#123169)
via llvm-commits
- [llvm] [MachinePipeliner] Remove UB from tests (NFC) (PR #123169)
Ryotaro Kasuga via llvm-commits
- [llvm] Stop abusing Twine in DiagnosticInfo (PR #136371)
Justin Bogner via llvm-commits
- [llvm] [AMDGPU] fix up vop3p gisel errors (PR #136262)
via llvm-commits
- [llvm] [COFF] Preserve UniqueID used to create MCSectionCOFF (PR #123869)
Haohai Wen via llvm-commits
- [llvm] [PseudoProbe] Add PseudoProbeDescUpdatePass (PR #99839)
Haohai Wen via llvm-commits
- [clang] [llvm] [clang][AVR] Improve compatibility of inline assembly with avr-gcc (PR #136534)
Ben Shi via llvm-commits
- [clang] [llvm] DO NOT MERGE: Identify places that need reserve. (PR #136543)
Kazu Hirata via llvm-commits
- [llvm] [LoongArch] Pre-commit for widen shuffle mask (PR #136544)
via llvm-commits
- [llvm] [MIPS]Remove unnecessary SLL instructions on MIPS64el (PR #109386)
via llvm-commits
- [llvm] 4853bf0 - [LoongArch] Lower build_vector to broadcast load if possible (#135896)
via llvm-commits
- [llvm] [LoongArch] Lower build_vector to broadcast load if possible (PR #135896)
via llvm-commits
- [llvm] 053451c - [RISCV] Handle scalarized reductions in getArithmeticReductionCost
Luke Lau via llvm-commits
- [llvm] [RISCV] Cost ordered bf16/f16 w/ zvfhmin reductions as invalid (PR #114250)
Luke Lau via llvm-commits
- [llvm] [HEXAGON] [MachinePipeliner] Fix the DAG in case of dependent phis. (PR #135925)
Abinaya Saravanan via llvm-commits
- [llvm] [IRCE] Fix '"Instruction does not dominate all uses!" after IRCE pass #63984' (PR #136505)
Nikita Popov via llvm-commits
- [llvm] [Hexagon] Handle Call Operand vxi1 in Hexagon without HVX Enabled (PR #136546)
via llvm-commits
- [llvm] [SDAG] Handle insert_subvector in isKnownNeverNaN (PR #131989)
Simon Pilgrim via llvm-commits
- [llvm] [X86] Check for AMXTile (PR #136507)
Simon Pilgrim via llvm-commits
- [llvm] 47ca7f1 - [X86] Remove unused BitVector TILERegs (NFC) (#136508)
via llvm-commits
- [llvm] [X86] Remove unused BitVector TILERegs (NFC) (PR #136508)
Simon Pilgrim via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Matt Arsenault via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Matt Arsenault via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Min-Yih Hsu via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Min-Yih Hsu via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Min-Yih Hsu via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Min-Yih Hsu via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Min-Yih Hsu via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Matt Arsenault via llvm-commits
- [llvm] [llvm-mca][FeatureRequest] Itimeline graph, note source of delay for each instruction (PR #136423)
Andrea Di Biagio via llvm-commits
- [llvm] [CostModel] Remove optional from InstructionCost::getValue() (PR #135596)
Simon Pilgrim via llvm-commits
- [llvm] [LoopVectorizer] Prune VFs based on plan register pressure (PR #132190)
Luke Lau via llvm-commits
- [llvm] [llvm] Use llvm::SmallVector::pop_back_val (NFC) (PR #136533)
Matt Arsenault via llvm-commits
- [llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)
via llvm-commits
- [llvm] [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #122741)
Matt Arsenault via llvm-commits
- [llvm] [X86][Combine] Ensure single use chain in extract-load combine (PR #136520)
Simon Pilgrim via llvm-commits
- [llvm] CodeGen: Add ISD::AssertNoFPClass (PR #135946)
Matt Arsenault via llvm-commits
- [llvm] [RISCV] Sink vp.splat operands of VP intrinsic. (PR #133245)
Luke Lau via llvm-commits
- [llvm] [X86][SelectionDAG] Fix the Gather's base and index by modifying the Scale value (PR #134979)
Simon Pilgrim via llvm-commits
- [llvm] [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (PR #136551)
Christudasan Devadasan via llvm-commits
- [llvm] [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (PR #136552)
Liao Chunyu via llvm-commits
- [llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)
Luke Lau via llvm-commits
- [llvm] [InstCombine] Fold tan(x) * cos(x) => sin(x) (PR #136319)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] add noalias.addrspace attribute for store and load (PR #136553)
via llvm-commits
- [llvm] insert readfirstlane in the function returns in sgpr (PR #135326)
Matt Arsenault via llvm-commits
- [llvm] [SDAG] Make Select-with-Identity-Fold More Flexible; NFC (PR #136554)
Marius Kamp via llvm-commits
- [llvm] [X86] Distribute Certain Bitwise Operations over SELECT (PR #136555)
Marius Kamp via llvm-commits
- [llvm] InstCombine: Fold samesign ult to slt with added constant when the range is known (PR #134556)
Rajagopalan Gangadharan via llvm-commits
- [llvm] c347ad2 - [RISCV][NFC] Delete RISCVAsmParser::parsePseudoQCJumpSymbol (#136552)
via llvm-commits
- [clang] [llvm] Add smcntrpmf extension (PR #136556)
Liao Chunyu via llvm-commits
- [llvm] [RISCV] Widen i1 AnyOf reductions (PR #134898)
Luke Lau via llvm-commits
- [llvm] [RISCV] Add range metadata for atomic load of boolean type. (PR #136502)
Sam Elliott via llvm-commits
- [llvm] [AMDGPU] Insert readfirstlane in the function returns in sgpr. (PR #135326)
Christudasan Devadasan via llvm-commits
- [llvm] 940108b - [AMDGPU][NewPM] Make the pass flow consistent with the legacy pipeline. (#136551)
via llvm-commits
- [llvm] [llvm-extract] support unnamed bbs. (PR #135140)
Benjamin Maxwell via llvm-commits
- [llvm] Added APInt::clearBits() method #136550 (PR #136557)
via llvm-commits
- [llvm] [ConstraintElim] Add facts about non-poison intrinsics on demand (PR #136558)
Yingwei Zheng via llvm-commits
- [llvm] [RISCV] Remove `AND` mask generated by `( zext ( atomic_load ) )` by replacing the load with `zextload` for orderings not stronger then monotonic. (PR #136502)
Jan Górski via llvm-commits
- [llvm] [AMDGPU] Implement vop3p complex pattern optmization for gisel (PR #130234)
Matt Arsenault via llvm-commits
- [llvm] [GlobalISel] Introduce `G_POISON` (PR #127825)
Matt Arsenault via llvm-commits
- [llvm] [InstSimplify] Fold `getelementptr inbounds null, idx -> null` (PR #130742)
Madhur Amilkanthwar via llvm-commits
- [llvm] [GlobalISel] Add `combine` action for C++ combine rules (PR #135941)
Matt Arsenault via llvm-commits
- [llvm] [LangRef][IR] Fix default AS documentation for allocas without explicit AS (PR #135942)
Matt Arsenault via llvm-commits
- [llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)
Matt Arsenault via llvm-commits
- [llvm] [CodeGenPrepare] Unfold slow ctpop when used in power-of-two test (PR #102731)
Matt Arsenault via llvm-commits
- [llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)
Matt Arsenault via llvm-commits
- [llvm] [LLVM][ISel][AArch64 Remove AArch64ISD::FCM##z nodes. (PR #135817)
Paul Walker via llvm-commits
- [llvm] [llvm] Support multiple save/restore points in mir (PR #119357)
Matt Arsenault via llvm-commits
- [llvm] [AArch64][GlobalISel] Adopt some Ld* patterns to reduce codegen regressions (PR #135492)
Matt Arsenault via llvm-commits
- [libcxxabi] [lldb] [llvm] [lldb] Add new per-language frame-format variables for formatting function names (PR #131836)
Michael Buch via llvm-commits
- [llvm] [DAGCombiner] Option --combiner-select-seq (PR #134813)
Matt Arsenault via llvm-commits
- [llvm] [MachinePipeliner] Add validation for missed dependencies (PR #135148)
Ryotaro Kasuga via llvm-commits
- [llvm] [VPlan] Add VPInstruction::StepVector and use it in VPWidenIntOrFpInductionRecipe (PR #129508)
Luke Lau via llvm-commits
- [llvm] Expanding the Histogram Intrinsic (PR #127399)
via llvm-commits
- [llvm] [lldb][LoongArch] Fix expression function call failure (PR #136563)
via llvm-commits
- [llvm] [BOLT][NFCI] Emit uniform diagnostics in DataAggregator (PR #136530)
Amir Ayupov via llvm-commits
- [flang] [llvm] [mlir] [MLIR][OpenMP] Lowering nontemporal clause to LLVM IR for SIMD directive (PR #118751)
Kaviya Rajendiran via llvm-commits
- [llvm] [AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (PR #124995)
Matt Arsenault via llvm-commits
- [llvm] [AMDGPU] Implement IR expansion for frem instruction (PR #130988)
Matt Arsenault via llvm-commits
- [llvm] [CodeGen][NPM] Update BranchFolderLegacy make tail merge configurable via flag (PR #135277)
Mikhail R. Gadelha via llvm-commits
- [llvm] [SystemZ] Add a SystemZ specific pre-RA scheduling strategy. (PR #135076)
Matt Arsenault via llvm-commits
- [llvm] 788b50a - [X86] Add test coverage for #136368
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Matt Arsenault via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Matt Arsenault via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Matt Arsenault via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
Simon Pilgrim via llvm-commits
- [llvm] [SelectionDAG][X86] Fold `sub(x, mul(divrem(x,y)[0], y))` to `divrem(x, y)[1]` (PR #136565)
via llvm-commits
- [llvm] InstCombine: Avoid counting uses of constants (PR #136566)
Matt Arsenault via llvm-commits
- [llvm] [AArch64][GlobalISel] Perfect Shuffles (PR #106446)
David Green via llvm-commits
- [clang] [llvm] [SROA] Vector promote some memsets (PR #133301)
via llvm-commits
- [llvm] [TTI] Constify BasicTTIImplBase::thisT() (PR #136567)
Sergei Barannikov via llvm-commits
- [llvm] [WIP][AMDGPU] Improve the handling of `inreg` arguments (PR #133614)
Shilei Tian via llvm-commits
- [llvm] [Analysis] Add DebugInfoCache analysis (PR #118629)
Artem Pianykh via llvm-commits
- [llvm] f12078e - [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#122741)
via llvm-commits
- [clang] [llvm] [RISCV] Add Andes XAndesperf (Andes Performance) extension. (PR #135110)
Jim Lin via llvm-commits
- [llvm] [Coro] Amortize debug info processing cost in CoroSplit (PR #109032)
Artem Pianykh via llvm-commits
- [llvm] [BOLT][AArch64] Support for pointer authentication (v2) (PR #120064)
Anatoly Trosinenko via llvm-commits
- [clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of global constants (PR #134399)
Nick Sarnie via llvm-commits
- [clang] [llvm] [DirectX] add Function name to DiagnosticInfoUnsupported Msg in DXILOpLowering (PR #136234)
Chris B via llvm-commits
- [llvm] 111af76 - [DirectX] add Function name to DiagnosticInfoUnsupported Msg in DXILOpLowering (#136234)
via llvm-commits
- [llvm] [AMDGPU] Skip handling of non-byte types in promote alloca. (PR #128769)
Sumanth Gundapaneni via llvm-commits
- [llvm] [LiveVariables] Mark use as implicit-def if defined at instr (PR #119446)
Sumanth Gundapaneni via llvm-commits
- [llvm] [Offload] Implement the remaining initial Offload API (PR #122106)
Callum Fare via llvm-commits
- [llvm] [SPARC] Use lzcnt to implement CTLZ when we have VIS3 (PR #135715)
Rainer Orth via llvm-commits
- [llvm] [DirectX] legalize memset (PR #136244)
Chris B via llvm-commits
- [llvm] e18a77c - Revert "[SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#122741)"
Nico Weber via llvm-commits
- [llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)
Brox Chen via llvm-commits
- [llvm] [VPlan] Also duplicated scalar-steps when it enables sinking scalars. (PR #136021)
Florian Hahn via llvm-commits
- [llvm] [VPlan] Add exit phi operands during initial construction (NFC). (PR #136455)
via llvm-commits
- [llvm] [llvm] annotate interfaces in llvm/Support for DLL export (PR #136014)
Andrew Rogers via llvm-commits
- [llvm] [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (PR #136015)
Mircea Trofin via llvm-commits
- [llvm] cfc2b0d - [llvm] Use llvm::SmallVector::pop_back_val (NFC) (#136533)
via llvm-commits
- [llvm] e1bb7f6 - [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (#136456)
via llvm-commits
- [llvm] [LLVM][TableGen] Parameterize NumToSkip in DecoderEmitter (PR #136456)
Rahul Joshi via llvm-commits
- [llvm] [InstrRef] Preserve debug instr num in aarch64-ldst-opt. (PR #136009)
Jeremy Morse via llvm-commits
- [llvm] [JITLink][AArch32] Add explicit visibility macros to functions needed by unittests (PR #116557)
Andrew Rogers via llvm-commits
- [llvm] [LLVM] Pass correct target to LLVM_RUNTIMES_TARGET for runtimes (PR #136572)
Joseph Huber via llvm-commits
- [llvm] [AArch64] Replace 64-bit MADD with [SU]MADDL when possible (PR #135926)
Yuri Gribov via llvm-commits
- [llvm] 93b74f7 - [ctxprof] Scale up everything under a root by its `TotalRootEntryCount` (#136015)
via llvm-commits
- [compiler-rt] [llvm] [msan] Add experimental '-mllvm -msan-embed-faulting-instruction' and MSAN_OPTIONS=print_faulting_instruction (PR #136539)
Thurston Dang via llvm-commits
- [llvm] [NFC][LLVM][TableGen] Eliminate inheritance from std::vector (PR #136573)
Rahul Joshi via llvm-commits
- [llvm] [OpenMP] Remove dependency on LLVM include directory from DeviceRTL (PR #136359)
Shilei Tian via llvm-commits
- [llvm] [LLVM] Cleanup pass initialization for Analysis passes (PR #135858)
Rahul Joshi via llvm-commits
- [llvm] [PowerPC] Intrinsics and tests for dmr insert/extract (PR #135653)
Maryam Moghadas via llvm-commits
- [llvm] [TTI] Constify BasicTTIImplBase::thisT() (PR #136575)
Sergei Barannikov via llvm-commits
- [llvm] [BOLT] Do not return Def-ed registers from MCPlusBuilder::getUsedRegs (PR #129890)
Anatoly Trosinenko via llvm-commits
- [llvm] 76ced7f - [AMDGPU] Insert readfirstlane in the function returns in sgpr. (#135326)
via llvm-commits
- [llvm] [RISCV] Report error if Zilsd is used on RV32. (PR #136577)
Craig Topper via llvm-commits
- [llvm] [AMDGPU] Add SchedGroupBarrier::PACK for packed math (PR #132432)
Jeffrey Byrnes via llvm-commits
- [llvm] [PAC][InstCombine] Replace auth+sign with resign (PR #130807)
Anatoly Trosinenko via llvm-commits
- [llvm] [AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies (PR #131387)
via llvm-commits
- [clang] [llvm] [HLSL] Implement the `faceforward` intrinsic (PR #135878)
Farzon Lotfi via llvm-commits
- [llvm] b95ec24 - [SDAG] Handle insert_subvector in isKnownNeverNaN (#131989)
via llvm-commits
- [llvm] [libc][bazel] Add a helper library with all deps of generated headers. (PR #136582)
Alexey Samsonov via llvm-commits
- [llvm] [AMDGPU] Support alloca in AS0 (PR #136584)
Shilei Tian via llvm-commits
- [llvm] 5739a22 - [VPlan] Also duplicated scalar-steps when it enables sinking scalars. (#136021)
via llvm-commits
- [llvm] [AMDGPU][True16][CodeGen] update GFX11Plus codegen test with true16 flag (PR #135078)
Brox Chen via llvm-commits
- [llvm] [RISCV] Use ri.vzip2{a, b} for interleave2 if available (PR #136364)
Philip Reames via llvm-commits
- [llvm] [RISCV] Allow spilling to unused Zcmp Stack (PR #125959)
Craig Topper via llvm-commits
- [llvm] [RISCV] Lower SEW<=32 vector_deinterleave(2) via vunzip2{a, b} (PR #136463)
Philip Reames via llvm-commits
- [llvm] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)
Shilei Tian via llvm-commits
- [llvm] [DebugInfo][DWARF] Emit DW_AT_abstract_origin for concrete/inlined DW_TAG_lexical_blocks (PR #136205)
David Blaikie via llvm-commits
- [llvm] 3e5a9d9 - [VPlan] Rename setFlags -> applyFlags (NFC).
Florian Hahn via llvm-commits
- [llvm] [VPlan] Manage instruction medata in VPlan. (PR #135272)
Florian Hahn via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Philip Reames via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Philip Reames via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Philip Reames via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Philip Reames via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Alexey Bataev via llvm-commits
- [llvm] [SLP]Model single unique value insert + shuffle as splat + select, where profitable (PR #136590)
Philip Reames via llvm-commits
- [llvm] [LLVM] Update handling of default runtime targets (PR #136591)
Joseph Huber via llvm-commits
- [llvm] [VPlan] Remove ILV::sinkScalarOperands. (PR #136023)
Florian Hahn via llvm-commits
- [llvm] [llvm] Construct SmallVector with iterator ranges (NFC) (PR #136460)
David Blaikie via llvm-commits
- [llvm] [VPlan] Impl VPlan-based pattern match for ExtendedRed and MulAccRed (PR #113903)
Florian Hahn via llvm-commits
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- [llvm] [CodeExtractor] Improve debug info for input values. (PR #136016)
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- [llvm] 8f8853a - [RISCV] Add ISel patterns for Xqcia instructions (#136548)
via llvm-commits
- [llvm] [DAGCombiner][RISCV] Add target hook to decide hoisting LogicOp with extension (PR #136677)
Jim Lin via llvm-commits
- [llvm] [AMDGPU] Reapply patch 135326 (PR #136678)
Pankaj Dwivedi via llvm-commits
- [llvm] [AArch64] Fix tryToConvertShuffleOfTbl2ToTbl4 with non-buildvector input operands. (PR #135961)
Nashe Mncube via llvm-commits
- [llvm] [LV] Add support for partial reductions without a binary op (PR #133922)
Florian Hahn via llvm-commits
- [llvm] [loop-vectorize] Fix crash when using types that aren't known scale factors (PR #136680)
Nicholas Guy via llvm-commits
- [llvm] a095ebc - [LLVM][CostModel][AArch64] Remove magic numbers from f16 vector compares. (#135795)
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- [llvm] [LLVM][CostModel][AArch64] Remove magic numbers from f16 vector compares. (PR #135795)
Paul Walker via llvm-commits
- [llvm] [AArch64] Add tablegen patterns for i8 and i16 vector insert/extract pairs (PR #136091)
Nashe Mncube via llvm-commits
- [llvm] [LoopVersioningLICM] Only mark pointers with generated checks as noalias (PR #135168)
John Brawn via llvm-commits
- [llvm] [VPlan] Fix MayReadFromMemory/MayWriteToMemory on VPWidenIntrinsicRecipe (PR #136684)
Luke Lau via llvm-commits
- [llvm] [LLVM][CodeGen][AArch64] Don't scalarise v8{f16,bf16} vsetcc operations. (PR #135398)
Paul Walker via llvm-commits
- [llvm] [LangRef] Add a description of the semantics of call signatures. (PR #136189)
Mehdi Amini via llvm-commits
- [llvm] [CMake] Only export the LLVM_LINK_LLVM_DYLIB setting if not yet set (PR #135570)
Jonas Rembser via llvm-commits
- [llvm] [llvm-cov] Fix branch counts of template functions (second attempt) (PR #135074)
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- [llvm] [Support] Use absolute paths for include filenames (PR #136687)
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- [llvm] [DebugInfo] Handle additional types of stores in assignment tracking (PR #129070)
Stephen Tozer via llvm-commits
- [llvm] 1a48e1d - [AMDGPU] Do not fold COPY with implicit operands (#136003)
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- [compiler-rt] [llvm] [TySan] Add option to outline instrumentation (PR #120582)
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- [llvm] [GlobalISel]: G_UNMERGE_VALUES for vectors with different element sizes (PR #133335)
Robert Imschweiler via llvm-commits
- [llvm] [MachinePipeliner] Use AliasAnalysis properly when analyzing loop-carried dependencies (PR #136691)
Ryotaro Kasuga via llvm-commits
- [llvm] a25fdd7 - Reapply "[AMDGPU] Insert readfirstlane in the function returns in sgpr." (#136678)
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- [llvm] [RISCV][NFC] Convert some predicates to TIIPredicate (PR #129658)
Pengcheng Wang via llvm-commits
- [llvm] [ConstraintElim] Add facts implied by intrinsics if they are used by other constraints (PR #80121)
Yingwei Zheng via llvm-commits
- [llvm] e428afd - [gn build] Port c3f815ba82de
LLVM GN Syncbot via llvm-commits
- [compiler-rt] [llvm] [MC/DC][Coverage] Enable profile correlation for MC/DC (PR #136437)
Roman Beliaev via llvm-commits
- [clang] [llvm] Add Support for Ziccamoc (PR #136694)
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- [polly] [RemoveDI][Polly] Migrate to adapt to the new DebugRecord format in more areas (PR #135935)
Karthika Devi C via llvm-commits
- [llvm] [AMDGPU][InsertWaitCnts] Add test for global_wb/inv/wbinv tracking (PR #135339)
Pierre van Houtryve via llvm-commits
- [llvm] 47903e3 - [AMDGPU][InsertWaitCnts] Add test for global_wb/inv/wbinv tracking (#135339)
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- [llvm] [AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (PR #135340)
Pierre van Houtryve via llvm-commits
- [llvm] ec3a905 - [AMDGPU][InsertWaitCnts] Track global_wb/inv/wbinv (#135340)
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- [llvm] 2b71269 - [SelectionDAG][X86] Fold `sub(x, mul(divrem(x, y)[0], y))` to `divrem(x, y)[1]` (#136565)
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- [llvm] [CostModel] Plumb CostKind into getExtractWithExtendCost (PR #135523)
David Green via llvm-commits
- [llvm] dba8acd - Revert "[ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)"
Hans Wennborg via llvm-commits
- [llvm] [InstCombine] Infer exact for lshr by cttz (PR #136696)
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- [clang] [llvm] [SYCL] Add SYCL property set registry class (PR #136697)
Justin Cai via llvm-commits
- [llvm] cfeaa39 - Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
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- [llvm] d20604e - [CostModel] Plumb CostKind into getExtractWithExtendCost (#135523)
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- [llvm] Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (PR #136701)
zhijian lin via llvm-commits
- [llvm] [X86][GlobalIsel] add strictfp attribute from ir in mir (PR #136702)
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- [libcxx] [llvm] [libc++] Implement P3379R0 Constrain `std::expected` equality operators (PR #135759)
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- [llvm] Remove an incorrect assert in MFMASmallGemmSingleWaveOpt. (PR #130131)
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- [llvm] 278062f - [CVP] Add test showing how a call-site range can pessimize opt (NFC)
Nikita Popov via llvm-commits
- [llvm] d51b278 - [IR] Intersect call and fn range in CallBase::getRange()
Nikita Popov via llvm-commits
- [llvm] [AArch64] Merge scaled and unscaled narrow zero stores (PR #136705)
Guy David via llvm-commits
- [llvm] 980531c - [VPlan] Fix MayReadFromMemory/MayWriteToMemory on VPWidenIntrinsicRecipe (#136684)
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- [llvm] c5a5f43 - Reapply [ValueTracking] Drop ucmp/scmp from getIntrinsicRange() (NFCI)
Nikita Popov via llvm-commits
- [compiler-rt] [compiler-rt][sanitizer] fix msghdr for musl (PR #136195)
Deák Lajos via llvm-commits
- [llvm] [AARch64] Funnel Shift now uses rev32/rev64 instructions (PR #136707)
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- [llvm] [VPlan] Manage instruction metadata in VPlan. (PR #135272)
Florian Hahn via llvm-commits
- [llvm] [AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (PR #130933)
Nicholas Guy via llvm-commits
- [llvm] [VPlan] Introduce VPlanConstantFolder (PR #125365)
Ramkumar Ramachandra via llvm-commits
- [llvm] [RISCV] Add codegen support for ri.vinsert.v.x and ri.vextract.x.v (PR #136708)
Philip Reames via llvm-commits
- [llvm] [LV] Improve code in selectInterleaveCount (NFC) (PR #128002)
Ramkumar Ramachandra via llvm-commits
- [flang] [llvm] [flang][OpenMP] Introduce OmpHintClause, simplify OmpAtomicClause (PR #136311)
Tom Eccles via llvm-commits
- [llvm] [LAA] Hoist setting condition for RT-checks (PR #128045)
Ramkumar Ramachandra via llvm-commits
- [llvm] 901ac60 - [RISCV] Use ri.vzip2{a,b} for interleave2 if available (#136364)
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- [llvm] [LV][LAA][NFC]Add a test with non-power-of-2 store-load forward distance, NFC (PR #136710)
Alexey Bataev via llvm-commits
- [llvm] [docs][CoC] Update verbiage about appeal process (PR #136715)
Cyndy Ishida via llvm-commits
- [llvm] [X86][GlobalIsel] support G_FABS for f80 (PR #136718)
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- [lld] [wasm-ld] Refactor WasmSym from static globals to per-link context (PR #134970)
Anutosh Bhat via llvm-commits
- [llvm] c607180 - [docs] Fix typo in GitHub.rst
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- [clang] [llvm] [clang][OpenMP] New OpenMP 6.0 threadset clause (PR #135807)
Alexey Bataev via llvm-commits
- [llvm] AMDGPU/GlobalISel: add RegBankLegalize rules for bitfield extract (PR #132381)
Petar Avramovic via llvm-commits
- [llvm] [BOLT][test] Resolve symlink for nm tool (NFC) (PR #136722)
YongKang Zhu via llvm-commits
- [compiler-rt] [TySan] Fix false positives with derived classes (PR #126260)
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- [llvm] a5a6ae1 - [docs][CoC] Update verbiage about appeal process (#136715)
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- [llvm] [DAG] shouldReduceLoadWidth - add optional<unsigned> byte offset argument (PR #136723)
Simon Pilgrim via llvm-commits
- [llvm] [LLVM][TableGen] Do not test fixed opcode value in DecoderEmitter tests (PR #136724)
Rahul Joshi via llvm-commits
- [llvm] [BOLT] Gadget scanner: analyze functions without CFG information (PR #133461)
Anatoly Trosinenko via llvm-commits
- [llvm] [LV] Fix missing entry in willGenerateVectors (PR #136712)
Ramkumar Ramachandra via llvm-commits
- [llvm] [RISCV][TTI] Use processShuffleMask for shuffle legalization estimate (PR #136191)
Philip Reames via llvm-commits
- [llvm] c049583 - [llvm] add LLVM_ABI_FRIEND macro for friend function decls (#136595)
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- [llvm] f52b01b - [SLP][NFC]Rename functions/variables, limit visibility to meet the coding standards, NFC
Alexey Bataev via llvm-commits
- [llvm] [RISCV] Add disjoint or patterns for vwadd[u].vv (PR #136716)
Luke Lau via llvm-commits
- [llvm] [RISCV] Add branch folding before branch relaxation (PR #134760)
Philip Reames via llvm-commits
- [clang] [llvm] [openmp] [OpenMP] Change build of OpenMP device runtime to be a separate runtime (PR #136729)
Joseph Huber via llvm-commits
- [llvm] [HLSL] Analyze updateCounter usage (PR #135669)
Ashley Coleman via llvm-commits
- [llvm] [NFC] Add a pre- commit test case for Patch https://github.com/llvm/llvm-project/pull/111696 (PR #136730)
zhijian lin via llvm-commits
- [llvm] [NFC][AArch64][GlobalISel] Add test coverage for vector store legalization (PR #134904)
Tobias Stadler via llvm-commits
- [llvm] [BOLT] Improve profile quality reporting (PR #130810)
via llvm-commits
- [llvm] 1c722fc - [RISCV][TTI] Use processShuffleMask for shuffle legalization estimate (#136191)
via llvm-commits
- [llvm] remove 'movt' if there is no user of it (PR #136735)
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- [compiler-rt] [compiler-rt] Make sure __clzdi2 doesn't call itself recursively on sparc64 (PR #136737)
via llvm-commits
- [llvm] 7c4cb0e - Fix build error introduced by 1c722fc
Philip Reames via llvm-commits
- [llvm] [NFC][AArch64][GlobalISel] Add test coverage for vector load/store legalization (PR #134904)
Matt Arsenault via llvm-commits
- [llvm] 5ebf08c - [DirectX] Allow llvm lifetime intrinsics to pass on to the DirectX backend (#136622)
via llvm-commits
- [llvm] fcb3097 - [LLVM][TableGen] Do not test fixed opcode value in DecoderEmitter tests (#136724)
via llvm-commits
- [llvm] b5eae19 - [flang][OpenMP] Introduce OmpHintClause, simplify OmpAtomicClause (#136311)
via llvm-commits
- [flang] [llvm] [flang][OpenMP] Extend common::AtomicDefaultMemOrderType enumeration (PR #136312)
Krzysztof Parzyszek via llvm-commits
- [llvm] [AArch64][SME] Allow spills of ZT0 around SME ABI routines again (PR #136726)
Benjamin Maxwell via llvm-commits
- [clang] [llvm] [OpenMP] Update the bitcode library install and search path (PR #136754)
Joseph Huber via llvm-commits
- [llvm] [JumpThreading] Do not unfold select if block has address taken and used (PR #135106)
Weihang Fan via llvm-commits
- [llvm] [LAA] Improve convergent tests (PR #136758)
Ramkumar Ramachandra via llvm-commits
- [llvm] [llvm] Add support for llvm IR atomicrmw fminimum/fmaximum instructions (PR #136759)
Jonathan Thackray via llvm-commits
- [compiler-rt] [ASan] Prevent ASan/LSan deadlock by preloading modules before error reporting (PR #131756)
David Justo via llvm-commits
- [llvm] [RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (PR #136762)
Craig Topper via llvm-commits
- [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space [1/2] (PR #135444)
via llvm-commits
- [clang] [llvm] [mlir] [NVPTX] Add support for Shared Cluster Memory address space [2/2] (PR #136768)
via llvm-commits
- [lld] [LLD][COFF] add __{data,bss}_{start,end}__ symbols for Cygwin support (PR #136180)
via llvm-commits
- [clang] [llvm] Reland "[HLSL][RootSignature] Implement initial parsing of the descriptor table clause params" (PR #136740)
Ashley Coleman via llvm-commits
- [llvm] d6a68be - [NVPTX] Add support for Shared Cluster Memory address space [1/2] (#135444)
via llvm-commits
- [llvm] [NVPTX] support packed f32 instructions for sm_100+ (PR #126337)
Alex MacLean via llvm-commits
- [llvm] a2be454 - [NVPTX] Use v2.u64 to load/store 128-bit values (#136638)
via llvm-commits
- [llvm] [AMDGPU] Fix for 131386 by reducing implicit definitions on register restoration (PR #133986)
Krzysztof Drewniak via llvm-commits
- [llvm] a7dcedc - [RISCV] Add initial batch of test coverage for zvqdotq codegen
Philip Reames via llvm-commits
- [llvm] [NVPTX] Fix ptxas tests from #135444 (PR #136782)
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- [llvm] 8dbf92e - [NVPTX] Fix ptxas tests from #135444 (#136782)
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- [lldb] [llvm] Add RISC-V CPU type and CPU subtype to llvm & lldb (PR #136785)
Jonas Devlieghere via llvm-commits
- [llvm] [DirectX] Fix shader flag version-checking logic to match DXC (PR #136787)
Deric C. via llvm-commits
- [llvm] AMDGPU/MC: Fix emitting absolute expressions (PR #136789)
Nicolai Hähnle via llvm-commits
- [clang] [llvm] User/raoanag/refract (PR #136026)
via llvm-commits
- [llvm] 3d04da5 - [NVPTX] Add support for Shared Cluster Memory address space [2/2] (#136768)
via llvm-commits
- [llvm] [NFCI] Move ProfOStream from InstrProfWriter.cpp to InstrProf.h/cpp (PR #136791)
Mingming Liu via llvm-commits
- [llvm] [Offload] Fix handling of 'bare' mode when environment missing (PR #136794)
Joseph Huber via llvm-commits
- [llvm] [InlineSpiller] Check rematerialization before folding operand (PR #134015)
via llvm-commits
- [llvm] Revert "[X86][APX] Support peephole optimization with CCMP instruction (#129994)" (PR #136796)
Feng Zou via llvm-commits
- [llvm] 2484060 - [RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
via llvm-commits
- [llvm] [RISCV] Return false for Zalasr load/store in isWorthFoldingAdd. (PR #136799)
Craig Topper via llvm-commits
- [llvm] 122e515 - gn build: Port d1cce66469d0 more
Peter Collingbourne via llvm-commits
- [llvm] [Utils][vim] Add missing hihlights for disjoint (PR #136801)
Jim Lin via llvm-commits
- [llvm] [libc] add uefi fullbuild to workflows (PR #131376)
Tristan Ross via llvm-commits
- [clang] [llvm] [Clang][OpenMP] Support for dispatch construct (Sema & Codegen) support (PR #131838)
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- [llvm] SelectionDAG: Add missing AddNodeIDCustom case for MDNodeSDNode. (PR #136805)
Peter Collingbourne via llvm-commits
- [llvm] 68d89e9 - [RISCV] Remove stale comment. NFC
Craig Topper via llvm-commits
- [llvm] [InstCombine] Offset both sides of an equality icmp (PR #134086)
via llvm-commits
- [llvm] 141c14c - [LoongArch] Pre-commit for widen shuffle mask (#136544)
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- [llvm] update_test_checks: Relax DIFile filename checks (PR #135692)
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Last message date:
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Archived on: Tue Apr 22 22:38:45 PDT 2025
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