[llvm] [RISCV] Add disjoint or patterns for vwadd[u].vv (PR #136716)

[Jim Lin via llvm-commits]

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@@ -912,6 +912,29 @@ defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
 
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjoint_VV<SDNode extop, string instruction_name> {
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tclin914 wrote:

This multiclass is both for VV and VX form. Should we rename it to with *_VV_VX suffix to be consistent with other patterns.

https://github.com/llvm/llvm-project/pull/136716