[llvm] [Xtensa] Implement Xtensa Region Protection Option and several other small Options. (PR #137135)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 24 01:20:30 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-mc
@llvm/pr-subscribers-backend-xtensa
Author: Andrei Safronov (andreisfr)
<details>
<summary>Changes</summary>
Implement support of the Xtensa Region Protection, Extended L32R, Data Cache, Relocatable Vector and MISC Special Registers Options.
---
Full diff: https://github.com/llvm/llvm-project/pull/137135.diff
11 Files Affected:
- (modified) llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp (+7-3)
- (modified) llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp (+11)
- (modified) llvm/lib/Target/Xtensa/XtensaFeatures.td (+25)
- (modified) llvm/lib/Target/Xtensa/XtensaInstrInfo.td (+58)
- (modified) llvm/lib/Target/Xtensa/XtensaRegisterInfo.td (+17-1)
- (modified) llvm/lib/Target/Xtensa/XtensaSubtarget.h (+5)
- (added) llvm/test/MC/Xtensa/dcache.s (+17)
- (added) llvm/test/MC/Xtensa/extendedl32r.s (+17)
- (added) llvm/test/MC/Xtensa/miscsr.s (+56)
- (added) llvm/test/MC/Xtensa/region_protect.s (+54)
- (added) llvm/test/MC/Xtensarvector.s (+17)
``````````diff
diff --git a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
index 6b355e6363b22..fcc1bb3765c81 100644
--- a/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
+++ b/llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp
@@ -114,9 +114,13 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
}
const MCPhysReg SRDecoderTable[] = {
- Xtensa::SAR, 3, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
- Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
- Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
+ Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2,
+ Xtensa::SAR, 3, Xtensa::BREG, 4, Xtensa::SAR, 3,
+ Xtensa::LITBASE, 5, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
+ Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
+ Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73,
+ Xtensa::MEMCTL, 97, Xtensa::VECBASE, 231, Xtensa::MISC0, 244,
+ Xtensa::MISC1, 345, Xtensa::MISC2, 246, Xtensa::MISC3, 247};
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
index 792faf811aca9..1c15048783db9 100644
--- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
+++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp
@@ -83,6 +83,17 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
case Xtensa::LEND:
case Xtensa::LCOUNT:
return FeatureBits[Xtensa::FeatureLoop];
+ case Xtensa::LITBASE:
+ return FeatureBits[Xtensa::FeatureExtendedL32R];
+ case Xtensa::MEMCTL:
+ return FeatureBits[Xtensa::FeatureDataCache];
+ case Xtensa::MISC0:
+ case Xtensa::MISC1:
+ case Xtensa::MISC2:
+ case Xtensa::MISC3:
+ return FeatureBits[Xtensa::FeatureMiscSR];
+ case Xtensa::VECBASE:
+ return FeatureBits[Xtensa::FeatureRelocatableVector];
case Xtensa::WINDOWBASE:
case Xtensa::WINDOWSTART:
return FeatureBits[Xtensa::FeatureWindowed];
diff --git a/llvm/lib/Target/Xtensa/XtensaFeatures.td b/llvm/lib/Target/Xtensa/XtensaFeatures.td
index 2a47214946401..55977277daf8e 100644
--- a/llvm/lib/Target/Xtensa/XtensaFeatures.td
+++ b/llvm/lib/Target/Xtensa/XtensaFeatures.td
@@ -67,3 +67,28 @@ def FeatureDiv32 : SubtargetFeature<"div32", "HasDiv32", "true",
"Enable Xtensa Div32 option">;
def HasDiv32 : Predicate<"Subtarget->hasDiv32()">,
AssemblerPredicate<(all_of FeatureDiv32)>;
+
+def FeatureRegionProtection : SubtargetFeature<"regprotect", "HasRegionProtection", "true",
+ "Enable Xtensa Region Protection option">;
+def HasRegionProtection : Predicate<"Subtarget->hasRegionProtection()">,
+ AssemblerPredicate<(all_of FeatureRegionProtection)>;
+
+def FeatureRelocatableVector : SubtargetFeature<"rvector", "HasRelocatableVector", "true",
+ "Enable Xtensa Relocatable Vector option">;
+def HasRelocatableVector : Predicate<"Subtarget->hasRelocatableVector()">,
+ AssemblerPredicate<(all_of FeatureRelocatableVector)>;
+
+def FeatureMiscSR : SubtargetFeature<"miscsr", "HasMiscSR", "true",
+ "Enable Xtensa Miscellaneous SR option">;
+def HasMiscSR : Predicate<"Subtarget->hasMiscSR()">,
+ AssemblerPredicate<(all_of FeatureMiscSR)>;
+
+def FeatureExtendedL32R : SubtargetFeature<"extendedl32r", "HasExtendedL32R", "true",
+ "Enable Xtensa Extended L32R option">;
+def HasExtendedL32R : Predicate<"Subtarget->hasExtendedL32R()">,
+ AssemblerPredicate<(all_of FeatureExtendedL32R)>;
+
+def FeatureDataCache : SubtargetFeature<"dcache", "HasDataCache", "true",
+ "Enable Xtensa Data Cache option">;
+def HasDataCache : Predicate<"Subtarget->hasDataCache()">,
+ AssemblerPredicate<(all_of FeatureDataCache)>;
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index 0bd3ba81340ff..2539e22adc80c 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -986,6 +986,64 @@ let Predicates = [HasDiv32] in {
def REMU : ArithLogic_RRR<0x0E, 0x02, "remu", urem>;
}
+//===----------------------------------------------------------------------===//
+// Region Protection feature instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasRegionProtection] in {
+ def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
+ "idtlb\t$s", []> {
+ let r = 0xC;
+ let t = 0x0;
+ }
+
+ def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "iitlb\t$s", []> {
+ let r = 0x4;
+ let t = 0x0;
+ }
+
+ def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "pdtlb\t$t, $s", []> {
+ let r = 0xD;
+ }
+
+ def PITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "pitlb\t$t, $s", []> {
+ let r = 0x5;
+ }
+
+ def RDTLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "rdtlb0\t$t, $s", []> {
+ let r = 0xB;
+ }
+
+ def RDTLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "rdtlb1\t$t, $s", []> {
+ let r = 0xF;
+ }
+
+ def RITLB0 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "ritlb0\t$t, $s", []> {
+ let r = 0x3;
+ }
+
+ def RITLB1 : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "ritlb1\t$t, $s", []> {
+ let r = 0x7;
+ }
+
+ def WDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "wdtlb\t$t, $s", []> {
+ let r = 0xE;
+ }
+
+ def WITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
+ "witlb\t$t, $s", []> {
+ let r = 0x6;
+ }
+}
+
//===----------------------------------------------------------------------===//
// DSP Instructions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
index 2a40431adc7f0..091f0d0f96262 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.td
@@ -84,10 +84,25 @@ def SAR : SRReg<3, "sar", ["SAR","3"]>;
// Boolean Register
def BREG : SRReg<4, "br", ["BR","4"]>;
+// Literal base
+def LITBASE : SRReg<5, "litbase", ["LITBASE", "5"]>;
+
// Windowed Register Option registers
def WINDOWBASE : SRReg<72, "windowbase", ["WINDOWBASE", "72"]>;
def WINDOWSTART : SRReg<73, "windowstart", ["WINDOWSTART", "73"]>;
+// Memory Control Register
+def MEMCTL : SRReg<97, "memctl", ["MEMCTL", "97"]>;
+
+// Vector base register
+def VECBASE : SRReg<231, "vecbase", ["VECBASE", "231"]>;
+
+// Xtensa Miscellaneous SR
+def MISC0 : SRReg<244, "misc0", ["MISC0", "244"]>;
+def MISC1 : SRReg<245, "misc1", ["MISC1", "245"]>;
+def MISC2 : SRReg<246, "misc2", ["MISC2", "246"]>;
+def MISC3 : SRReg<247, "misc3", ["MISC3", "247"]>;
+
// MAC16 Option registers
def ACCLO : SRReg<16, "acclo", ["ACCLO", "16"]>;
def ACCHI : SRReg<17, "acchi", ["ACCHI", "17"]>;
@@ -101,7 +116,8 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
def SR : RegisterClass<"Xtensa", [i32], 32, (add
- LBEG, LEND, LCOUNT, SAR, BREG, MR, WINDOWBASE, WINDOWSTART)>;
+ LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, MR, WINDOWBASE, WINDOWSTART,
+ MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
//===----------------------------------------------------------------------===//
// Boolean registers
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 227ce2134b33b..9909fb9ff4b37 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -77,6 +77,11 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
bool hasMul32() const { return HasMul32; }
bool hasMul32High() const { return HasMul32High; }
bool hasDiv32() const { return HasDiv32; }
+ bool hasRegionProtection() const { return HasRegionProtection; }
+ bool hasRelocatableVector() const { return HasRelocatableVector; }
+ bool hasMiscSR() const { return HasMiscSR; }
+ bool hasExtendedL32R() const { return HasExtendedL32R; }
+ bool hasDataCache() const { return HasDataCache; }
bool isWindowedABI() const { return hasWindowed(); }
// Automatically generated by tblgen.
diff --git a/llvm/test/MC/Xtensa/dcache.s b/llvm/test/MC/Xtensa/dcache.s
new file mode 100644
index 0000000000000..9baa4980a6107
--- /dev/null
+++ b/llvm/test/MC/Xtensa/dcache.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+dcache \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr a3, memctl
+
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr.memctl a3
+
+# CHECK-INST: xsr a3, memctl
+# CHECK: # encoding: [0x30,0x61,0x61]
+xsr a3, 97
diff --git a/llvm/test/MC/Xtensa/extendedl32r.s b/llvm/test/MC/Xtensa/extendedl32r.s
new file mode 100644
index 0000000000000..d13a6b751b0dc
--- /dev/null
+++ b/llvm/test/MC/Xtensa/extendedl32r.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+extendedl32r \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr a3, litbase
+
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr.litbase a3
+
+# CHECK-INST: xsr a3, litbase
+# CHECK: # encoding: [0x30,0x05,0x61]
+xsr a3, 5
diff --git a/llvm/test/MC/Xtensa/miscsr.s b/llvm/test/MC/Xtensa/miscsr.s
new file mode 100644
index 0000000000000..82954dfde19f2
--- /dev/null
+++ b/llvm/test/MC/Xtensa/miscsr.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+miscsr \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr a3, misc0
+
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr.misc0 a3
+
+# CHECK-INST: xsr a3, misc0
+# CHECK: # encoding: [0x30,0xf4,0x61]
+xsr a3, 244
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr a3, misc1
+
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr.misc1 a3
+
+# CHECK-INST: xsr a3, misc1
+# CHECK: # encoding: [0x30,0xf5,0x61]
+xsr a3, 245
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr a3, misc2
+
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr.misc2 a3
+
+# CHECK-INST: xsr a3, misc2
+# CHECK: # encoding: [0x30,0xf6,0x61]
+xsr a3, 246
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr a3, misc3
+
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr.misc3 a3
+
+# CHECK-INST: xsr a3, misc3
+# CHECK: # encoding: [0x30,0xf7,0x61]
+xsr a3, 247
diff --git a/llvm/test/MC/Xtensa/region_protect.s b/llvm/test/MC/Xtensa/region_protect.s
new file mode 100644
index 0000000000000..dfe30e93972b2
--- /dev/null
+++ b/llvm/test/MC/Xtensa/region_protect.s
@@ -0,0 +1,54 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+regprotect \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RRR
+# CHECK-INST: idtlb a3
+# CHECK: encoding: [0x00,0xc3,0x50]
+idtlb a3
+
+# Instruction format RRR
+# CHECK-INST: iitlb a3
+# CHECK: encoding: [0x00,0x43,0x50]
+iitlb a3
+
+# Instruction format RRR
+# CHECK-INST: pdtlb a3, a4
+# CHECK: encoding: [0x30,0xd4,0x50]
+pdtlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: pitlb a3, a4
+# CHECK: encoding: [0x30,0x54,0x50]
+pitlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: rdtlb0 a3, a4
+# CHECK: encoding: [0x30,0xb4,0x50]
+rdtlb0 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: rdtlb1 a3, a4
+# CHECK: encoding: [0x30,0xf4,0x50]
+rdtlb1 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: ritlb0 a3, a4
+# CHECK: encoding: [0x30,0x34,0x50]
+ritlb0 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: ritlb1 a3, a4
+# CHECK: encoding: [0x30,0x74,0x50]
+ritlb1 a3, a4
+
+# Instruction format RRR
+# CHECK-INST: wdtlb a3, a4
+# CHECK: encoding: [0x30,0xe4,0x50]
+wdtlb a3, a4
+
+# Instruction format RRR
+# CHECK-INST: witlb a3, a4
+# CHECK: encoding: [0x30,0x64,0x50]
+witlb a3, a4
diff --git a/llvm/test/MC/Xtensarvector.s b/llvm/test/MC/Xtensarvector.s
new file mode 100644
index 0000000000000..17481cc8b35d3
--- /dev/null
+++ b/llvm/test/MC/Xtensarvector.s
@@ -0,0 +1,17 @@
+# RUN: llvm-mc %s -triple=xtensa -show-encoding --mattr=+rvector \
+# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+.align 4
+
+# Instruction format RSR
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr a3, vecbase
+
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr.vecbase a3
+
+# CHECK-INST: xsr a3, vecbase
+# CHECK: # encoding: [0x30,0xe7,0x61]
+xsr a3, 231
``````````
</details>
https://github.com/llvm/llvm-project/pull/137135
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