[llvm] [RISCV] Support disjoint RISCVISD::OR_VL in combineOp_VLToVWOp_VL (PR #136820)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 23 00:08:15 PDT 2025
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/136820
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a separate patch due to the extends being sunk, see #136716.
>From 11693d36aa220ec39dfcd0c45db265388b287792 Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Wed, 23 Apr 2025 15:01:23 +0800
Subject: [PATCH] [RISCV] Support disjoint RISCVISD::OR_VL in
combineOp_VLToVWOp_VL
This handles combining fixed-length disjoint ors to vwadd[u].wv, as was done for scalable vectors in #86929.
vwadd[u].vv patterns need to be handled separately with a pattern in a separate patch due to the extends being sunk, see #136716.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 10 +++++++++-
.../CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll | 18 +++++++-----------
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index dadae2e71d44c..24c44262e9070 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16002,6 +16002,7 @@ struct NodeExtensionHelper {
case RISCVISD::VWADD_W_VL:
case RISCVISD::VWADDU_W_VL:
case ISD::OR:
+ case RISCVISD::OR_VL:
return RISCVISD::VWADD_VL;
case ISD::SUB:
case RISCVISD::SUB_VL:
@@ -16025,6 +16026,7 @@ struct NodeExtensionHelper {
case RISCVISD::VWADD_W_VL:
case RISCVISD::VWADDU_W_VL:
case ISD::OR:
+ case RISCVISD::OR_VL:
return RISCVISD::VWADDU_VL;
case ISD::SUB:
case RISCVISD::SUB_VL:
@@ -16082,6 +16084,7 @@ struct NodeExtensionHelper {
case ISD::ADD:
case RISCVISD::ADD_VL:
case ISD::OR:
+ case RISCVISD::OR_VL:
return SupportsExt == ExtKind::SExt ? RISCVISD::VWADD_W_VL
: RISCVISD::VWADDU_W_VL;
case ISD::SUB:
@@ -16272,6 +16275,8 @@ struct NodeExtensionHelper {
case RISCVISD::VFWADD_W_VL:
case RISCVISD::VFWSUB_W_VL:
return true;
+ case RISCVISD::OR_VL:
+ return Root->getFlags().hasDisjoint();
case ISD::SHL:
return Root->getValueType(0).isScalableVector() &&
Subtarget.hasStdExtZvbb();
@@ -16357,6 +16362,7 @@ struct NodeExtensionHelper {
case ISD::OR:
case RISCVISD::ADD_VL:
case RISCVISD::MUL_VL:
+ case RISCVISD::OR_VL:
case RISCVISD::VWADD_W_VL:
case RISCVISD::VWADDU_W_VL:
case RISCVISD::FADD_VL:
@@ -16573,6 +16579,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
case ISD::OR:
case RISCVISD::ADD_VL:
case RISCVISD::SUB_VL:
+ case RISCVISD::OR_VL:
case RISCVISD::FADD_VL:
case RISCVISD::FSUB_VL:
// add|sub|fadd|fsub-> vwadd(u)|vwsub(u)|vfwadd|vfwsub
@@ -16623,7 +16630,7 @@ NodeExtensionHelper::getSupportedFoldings(const SDNode *Root) {
/// Combine a binary or FMA operation to its equivalent VW or VW_W form.
/// The supported combines are:
-/// add | add_vl | or disjoint -> vwadd(u) | vwadd(u)_w
+/// add | add_vl | or disjoint | or_vl disjoint -> vwadd(u) | vwadd(u)_w
/// sub | sub_vl -> vwsub(u) | vwsub(u)_w
/// mul | mul_vl -> vwmul(u) | vwmul_su
/// shl | shl_vl -> vwsll
@@ -19459,6 +19466,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case RISCVISD::VWSUB_W_VL:
case RISCVISD::VWSUBU_W_VL:
return performVWADDSUBW_VLCombine(N, DCI, Subtarget);
+ case RISCVISD::OR_VL:
case RISCVISD::SUB_VL:
case RISCVISD::MUL_VL:
return combineOp_VLToVWOp_VL(N, DCI, Subtarget);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index 5e7d1b91d7892..4346e90a1f5f7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -883,11 +883,9 @@ define <4 x i32> @vwaddu_vv_disjoint_or_add(<4 x i8> %x.i8, <4 x i8> %y.i8) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8
-; CHECK-NEXT: vsll.vi v8, v10, 8
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v10, v8
-; CHECK-NEXT: vzext.vf4 v8, v9
-; CHECK-NEXT: vor.vv v8, v10, v8
+; CHECK-NEXT: vsll.vi v10, v10, 8
+; CHECK-NEXT: vzext.vf2 v11, v9
+; CHECK-NEXT: vwaddu.vv v8, v10, v11
; CHECK-NEXT: ret
%x.i16 = zext <4 x i8> %x.i8 to <4 x i16>
%x.shl = shl <4 x i16> %x.i16, splat (i16 8)
@@ -960,9 +958,8 @@ define <4 x i32> @vwadd_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
define <4 x i32> @vwaddu_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
; CHECK-LABEL: vwaddu_wv_disjoint_or:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v10, v9
-; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vwaddu.wv v8, v8, v9
; CHECK-NEXT: ret
%y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
%or = or disjoint <4 x i32> %x.i32, %y.i32
@@ -972,9 +969,8 @@ define <4 x i32> @vwaddu_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
define <4 x i32> @vwadd_wv_disjoint_or(<4 x i32> %x.i32, <4 x i16> %y.i16) {
; CHECK-LABEL: vwadd_wv_disjoint_or:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v10, v9
-; CHECK-NEXT: vor.vv v8, v8, v10
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vwadd.wv v8, v8, v9
; CHECK-NEXT: ret
%y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
%or = or disjoint <4 x i32> %x.i32, %y.i32
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