[llvm] [Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation (PR #135768)

[via llvm-commits]

https://github.com/yingopq updated https://github.com/llvm/llvm-project/pull/135768

>From 126d7ba4e1248cb51eb75c2e3408887bf8799cc5 Mon Sep 17 00:00:00 2001
From: Ying Huang <ying.huang at oss.cipunited.com>
Date: Tue, 15 Apr 2025 05:32:29 -0400
Subject: [PATCH] [Mips] Do not emit instruction teq if divisor is non-zero
 immediate value in FastISel implementation

Add a check before emitting the teq instruction to check whether
the divisor is a non-zero immediate value.

Fix #130629.
---
 llvm/lib/Target/Mips/MipsFastISel.cpp       |  5 ++-
 llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll | 43 +++++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletion(-)
 create mode 100644 llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll

diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index ec138fb3f1906..f3812d185ec92 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1947,7 +1947,10 @@ bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
     return false;
 
   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
-  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+  if (!isa<ConstantInt>(I->getOperand(1)) ||
+      dyn_cast<ConstantInt>(I->getOperand(1))->isZero()) {
+    emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+  }
 
   Register ResultReg = createResultReg(&Mips::GPR32RegClass);
   if (!ResultReg)
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll
new file mode 100644
index 0000000000000..e1653a83edc0b
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic | FileCheck %s
+
+define i32 @div_imm_non_zero(i32 signext %a) nounwind {
+; CHECK-LABEL: div_imm_non_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -8
+; CHECK-NEXT:    sw $4, 4($sp)
+; CHECK-NEXT:    lw $1, 4($sp)
+; CHECK-NEXT:    addiu $2, $zero, 1234
+; CHECK-NEXT:    div $zero, $1, $2
+; CHECK-NEXT:    mflo $2
+; CHECK-NEXT:    addiu $sp, $sp, 8
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    nop
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4
+  %0 = load i32, ptr %a.addr, align 4
+  %div = sdiv i32 %0, 1234
+  ret i32 %div
+}
+
+define i32 @div_imm_zero(i32 signext %a) nounwind {
+; CHECK-LABEL: div_imm_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $sp, $sp, -8
+; CHECK-NEXT:    sw $4, 4($sp)
+; CHECK-NEXT:    lw $1, 4($sp)
+; CHECK-NEXT:    addiu $2, $zero, 0
+; CHECK-NEXT:    div $zero, $1, $zero
+; CHECK-NEXT:    teq $zero, $zero, 7
+; CHECK-NEXT:    mflo $2
+; CHECK-NEXT:    addiu $sp, $sp, 8
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    nop
+entry:
+  %a.addr = alloca i32, align 4
+  store i32 %a, ptr %a.addr, align 4
+  %0 = load i32, ptr %a.addr, align 4
+  %div = sdiv i32 %0, 0
+  ret i32 %div
+}