[llvm] acc335b - [X86] Add build vector test patterns with only 2 unique scalars
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 24 03:50:32 PDT 2025
Author: Simon Pilgrim
Date: 2025-04-24T11:47:09+01:00
New Revision: acc335bfa7b00ab19bf9832870aaf207f587b48b
URL: https://github.com/llvm/llvm-project/commit/acc335bfa7b00ab19bf9832870aaf207f587b48b
DIFF: https://github.com/llvm/llvm-project/commit/acc335bfa7b00ab19bf9832870aaf207f587b48b.diff
LOG: [X86] Add build vector test patterns with only 2 unique scalars
Based off test coverage for #135753 - these should be lowered to BLEND(BROADCAST(X),BROADCAST(Y))
Added:
Modified:
llvm/test/CodeGen/X86/build-vector-128.ll
llvm/test/CodeGen/X86/build-vector-256.ll
llvm/test/CodeGen/X86/build-vector-512.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/build-vector-128.ll b/llvm/test/CodeGen/X86/build-vector-128.ll
index 30f55a1d41922..e2db8d4241420 100644
--- a/llvm/test/CodeGen/X86/build-vector-128.ll
+++ b/llvm/test/CodeGen/X86/build-vector-128.ll
@@ -410,6 +410,631 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
ret <16 x i8> %ins15
}
+; build vectors of repeated elements
+
+define <4 x float> @test_buildvector_4f32_2_var(float %a0, float %a1) {
+; SSE2-32-LABEL: test_buildvector_4f32_2_var:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_4f32_2_var:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movaps %xmm1, %xmm2
+; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_4f32_2_var:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_4f32_2_var:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movaps %xmm0, %xmm2
+; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[2,3]
+; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm1[0],xmm2[3]
+; SSE41-64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm0[0]
+; SSE41-64-NEXT: movaps %xmm2, %xmm0
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_4f32_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_4f32_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm2[0,1],xmm1[0],xmm2[3]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[0]
+; AVX-64-NEXT: retq
+ %v0 = insertelement <4 x float> poison, float %a0, i32 0
+ %v1 = insertelement <4 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <4 x float> %v1, float %a1, i32 2
+ %v3 = insertelement <4 x float> %v2, float %a0, i32 3
+ ret <4 x float> %v3
+}
+
+define <4 x float> @test_buildvector_4f32_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_4f32_2_load:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movaps %xmm1, %xmm2
+; SSE2-32-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-32-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_4f32_2_load:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-64-NEXT: movaps %xmm1, %xmm2
+; SSE2-64-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
+; SSE2-64-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_4f32_2_load:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE41-32-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE41-32-NEXT: movaps %xmm2, %xmm0
+; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; SSE41-32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_4f32_2_load:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE41-64-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE41-64-NEXT: movaps %xmm2, %xmm0
+; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
+; SSE41-64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[0]
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_4f32_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_4f32_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-64-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1],xmm0[0],xmm2[3]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
+; AVX-64-NEXT: retq
+ %a0 = load float, ptr %p0
+ %a1 = load float, ptr %p1
+ %v0 = insertelement <4 x float> poison, float %a0, i32 0
+ %v1 = insertelement <4 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <4 x float> %v1, float %a1, i32 2
+ %v3 = insertelement <4 x float> %v2, float %a0, i32 3
+ ret <4 x float> %v3
+}
+
+define <8 x i16> @test_buildvector_8i16_2_var(i16 %a0, i16 %a1) {
+; SSE2-32-LABEL: test_buildvector_8i16_2_var:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-32-NEXT: movdqa %xmm2, %xmm1
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_8i16_2_var:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movd %esi, %xmm1
+; SSE2-64-NEXT: movd %edi, %xmm0
+; SSE2-64-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-64-NEXT: movdqa %xmm2, %xmm1
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_8i16_2_var:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT: movd %eax, %xmm0
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT: pinsrw $1, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $2, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $3, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $4, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $5, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $6, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $7, %ecx, %xmm0
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_8i16_2_var:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movd %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $1, %esi, %xmm0
+; SSE41-64-NEXT: pinsrw $2, %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $3, %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $4, %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $5, %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $6, %edi, %xmm0
+; SSE41-64-NEXT: pinsrw $7, %esi, %xmm0
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_8i16_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: vmovd %eax, %xmm0
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_8i16_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovd %edi, %xmm0
+; AVX-64-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $2, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $3, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $4, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $7, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: retq
+ %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0
+ %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1
+ %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2
+ %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3
+ %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4
+ %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5
+ %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6
+ %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7
+ ret <8 x i16> %v7
+}
+
+define <8 x i16> @test_buildvector_8i16_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_8i16_2_load:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT: movzwl (%ecx), %ecx
+; SSE2-32-NEXT: movd %ecx, %xmm1
+; SSE2-32-NEXT: movzwl (%eax), %eax
+; SSE2-32-NEXT: movd %eax, %xmm0
+; SSE2-32-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-32-NEXT: movdqa %xmm2, %xmm1
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_8i16_2_load:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movzwl (%rsi), %eax
+; SSE2-64-NEXT: movd %eax, %xmm1
+; SSE2-64-NEXT: movzwl (%rdi), %eax
+; SSE2-64-NEXT: movd %eax, %xmm0
+; SSE2-64-NEXT: pshuflw {{.*#+}} xmm2 = xmm0[0,0,0,0,4,5,6,7]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE2-64-NEXT: movdqa %xmm2, %xmm1
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_8i16_2_load:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT: movzwl (%eax), %eax
+; SSE41-32-NEXT: movzwl (%ecx), %ecx
+; SSE41-32-NEXT: movd %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $1, %eax, %xmm0
+; SSE41-32-NEXT: pinsrw $2, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $3, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $4, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $5, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $6, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrw $7, %eax, %xmm0
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_8i16_2_load:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movzwl (%rsi), %eax
+; SSE41-64-NEXT: movzwl (%rdi), %ecx
+; SSE41-64-NEXT: movd %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $1, %eax, %xmm0
+; SSE41-64-NEXT: pinsrw $2, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $3, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $4, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $5, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $6, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrw $7, %eax, %xmm0
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_8i16_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: movzwl (%ecx), %ecx
+; AVX-32-NEXT: movzwl (%eax), %eax
+; AVX-32-NEXT: vmovd %eax, %xmm0
+; AVX-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_8i16_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: movzwl (%rsi), %eax
+; AVX-64-NEXT: movzwl (%rdi), %ecx
+; AVX-64-NEXT: vmovd %ecx, %xmm0
+; AVX-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: retq
+ %a0 = load i16, ptr %p0
+ %a1 = load i16, ptr %p1
+ %v0 = insertelement <8 x i16> poison, i16 %a0, i32 0
+ %v1 = insertelement <8 x i16> %v0, i16 %a1, i32 1
+ %v2 = insertelement <8 x i16> %v1, i16 %a0, i32 2
+ %v3 = insertelement <8 x i16> %v2, i16 %a0, i32 3
+ %v4 = insertelement <8 x i16> %v3, i16 %a0, i32 4
+ %v5 = insertelement <8 x i16> %v4, i16 %a0, i32 5
+ %v6 = insertelement <8 x i16> %v5, i16 %a0, i32 6
+ %v7 = insertelement <8 x i16> %v6, i16 %a1, i32 7
+ ret <8 x i16> %v7
+}
+
+define <16 x i8> @test_buildvector_16i8_2_var(i8 %a0, i8 %a1) {
+; SSE2-32-LABEL: test_buildvector_16i8_2_var:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; SSE2-32-NEXT: movdqa %xmm2, %xmm1
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-32-NEXT: movdqa %xmm0, %xmm3
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-32-NEXT: movdqa %xmm1, %xmm4
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
+; SSE2-32-NEXT: movdqa %xmm3, %xmm2
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_16i8_2_var:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movd %edi, %xmm0
+; SSE2-64-NEXT: movd %esi, %xmm1
+; SSE2-64-NEXT: movdqa %xmm1, %xmm2
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; SSE2-64-NEXT: movdqa %xmm0, %xmm3
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-64-NEXT: movdqa %xmm2, %xmm4
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE2-64-NEXT: movdqa %xmm3, %xmm1
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_16i8_2_var:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT: movd %eax, %xmm0
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT: pinsrb $1, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $2, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $3, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $4, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $5, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $6, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $7, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $8, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $9, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $10, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $11, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $12, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $13, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $14, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $15, %eax, %xmm0
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_16i8_2_var:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movd %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $1, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $2, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $3, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $4, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $5, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $6, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $7, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $8, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $9, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $10, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $11, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $12, %esi, %xmm0
+; SSE41-64-NEXT: pinsrb $13, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $14, %edi, %xmm0
+; SSE41-64-NEXT: pinsrb $15, %edi, %xmm0
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_16i8_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: vmovd %eax, %xmm0
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_16i8_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovd %edi, %xmm0
+; AVX-64-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $3, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $4, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $5, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $6, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $7, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $8, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $9, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $10, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $11, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $12, %esi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $13, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $14, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0
+; AVX-64-NEXT: retq
+ %v0 = insertelement <16 x i8> poison, i8 %a0, i8 0
+ %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 1
+ %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 2
+ %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 3
+ %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 4
+ %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 5
+ %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 6
+ %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 7
+ %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 8
+ %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 9
+ %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 10
+ %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 11
+ %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 12
+ %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 13
+ %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 14
+ %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 15
+ ret <16 x i8> %v15
+}
+
+define <16 x i8> @test_buildvector_16i8_2_load(ptr %p0, ptr %p1) {
+; SSE2-32-LABEL: test_buildvector_16i8_2_load:
+; SSE2-32: # %bb.0:
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE2-32-NEXT: movzbl (%ecx), %ecx
+; SSE2-32-NEXT: movd %ecx, %xmm0
+; SSE2-32-NEXT: movzbl (%eax), %eax
+; SSE2-32-NEXT: movd %eax, %xmm2
+; SSE2-32-NEXT: movdqa %xmm2, %xmm1
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
+; SSE2-32-NEXT: movdqa %xmm0, %xmm3
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-32-NEXT: movdqa %xmm1, %xmm4
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-32-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
+; SSE2-32-NEXT: movdqa %xmm3, %xmm2
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]
+; SSE2-32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-32-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; SSE2-32-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE2-32-NEXT: retl
+;
+; SSE2-64-LABEL: test_buildvector_16i8_2_load:
+; SSE2-64: # %bb.0:
+; SSE2-64-NEXT: movzbl (%rdi), %eax
+; SSE2-64-NEXT: movd %eax, %xmm0
+; SSE2-64-NEXT: movzbl (%rsi), %eax
+; SSE2-64-NEXT: movd %eax, %xmm1
+; SSE2-64-NEXT: movdqa %xmm1, %xmm2
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
+; SSE2-64-NEXT: movdqa %xmm0, %xmm3
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1],xmm3[2],xmm0[2],xmm3[3],xmm0[3],xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-64-NEXT: movdqa %xmm2, %xmm4
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1],xmm4[2],xmm3[2],xmm4[3],xmm3[3]
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
+; SSE2-64-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
+; SSE2-64-NEXT: movdqa %xmm3, %xmm1
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
+; SSE2-64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3]
+; SSE2-64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
+; SSE2-64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
+; SSE2-64-NEXT: retq
+;
+; SSE41-32-LABEL: test_buildvector_16i8_2_load:
+; SSE41-32: # %bb.0:
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; SSE41-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; SSE41-32-NEXT: movzbl (%ecx), %ecx
+; SSE41-32-NEXT: movzbl (%eax), %eax
+; SSE41-32-NEXT: movd %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $1, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $2, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $3, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $4, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $5, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $6, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $7, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $8, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $9, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $10, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $11, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $12, %ecx, %xmm0
+; SSE41-32-NEXT: pinsrb $13, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $14, %eax, %xmm0
+; SSE41-32-NEXT: pinsrb $15, %eax, %xmm0
+; SSE41-32-NEXT: retl
+;
+; SSE41-64-LABEL: test_buildvector_16i8_2_load:
+; SSE41-64: # %bb.0:
+; SSE41-64-NEXT: movzbl (%rsi), %ecx
+; SSE41-64-NEXT: movzbl (%rdi), %eax
+; SSE41-64-NEXT: movd %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $1, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $2, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $3, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $4, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $5, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $6, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $7, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $8, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $9, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $10, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $11, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $12, %ecx, %xmm0
+; SSE41-64-NEXT: pinsrb $13, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $14, %eax, %xmm0
+; SSE41-64-NEXT: pinsrb $15, %eax, %xmm0
+; SSE41-64-NEXT: retq
+;
+; AVX-32-LABEL: test_buildvector_16i8_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: movzbl (%ecx), %ecx
+; AVX-32-NEXT: movzbl (%eax), %eax
+; AVX-32-NEXT: vmovd %eax, %xmm0
+; AVX-32-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $2, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $4, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $5, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $6, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $9, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $13, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $14, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_16i8_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: movzbl (%rsi), %eax
+; AVX-64-NEXT: movzbl (%rdi), %ecx
+; AVX-64-NEXT: vmovd %ecx, %xmm0
+; AVX-64-NEXT: vpinsrb $1, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $7, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $8, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $11, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $12, %eax, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: vpinsrb $15, %ecx, %xmm0, %xmm0
+; AVX-64-NEXT: retq
+ %a0 = load i8, ptr %p0
+ %a1 = load i8, ptr %p1
+ %v0 = insertelement <16 x i8> poison, i8 %a0, i8 0
+ %v1 = insertelement <16 x i8> %v0, i8 %a1, i8 1
+ %v2 = insertelement <16 x i8> %v1, i8 %a0, i8 2
+ %v3 = insertelement <16 x i8> %v2, i8 %a0, i8 3
+ %v4 = insertelement <16 x i8> %v3, i8 %a0, i8 4
+ %v5 = insertelement <16 x i8> %v4, i8 %a0, i8 5
+ %v6 = insertelement <16 x i8> %v5, i8 %a0, i8 6
+ %v7 = insertelement <16 x i8> %v6, i8 %a1, i8 7
+ %v8 = insertelement <16 x i8> %v7, i8 %a1, i8 8
+ %v9 = insertelement <16 x i8> %v8, i8 %a0, i8 9
+ %v10 = insertelement <16 x i8> %v9, i8 %a1, i8 10
+ %v11 = insertelement <16 x i8> %v10, i8 %a1, i8 11
+ %v12 = insertelement <16 x i8> %v11, i8 %a1, i8 12
+ %v13 = insertelement <16 x i8> %v12, i8 %a0, i8 13
+ %v14 = insertelement <16 x i8> %v13, i8 %a0, i8 14
+ %v15 = insertelement <16 x i8> %v14, i8 %a0, i8 15
+ ret <16 x i8> %v15
+}
+
; PR30780
define <4 x i32> @test_buildvector_v4i32_splat_sext_i8(i8 %in) {
diff --git a/llvm/test/CodeGen/X86/build-vector-256.ll b/llvm/test/CodeGen/X86/build-vector-256.ll
index d2d7a194c7012..6c1cbfb4014b6 100644
--- a/llvm/test/CodeGen/X86/build-vector-256.ll
+++ b/llvm/test/CodeGen/X86/build-vector-256.ll
@@ -412,6 +412,353 @@ define <32 x i8> @test_buildvector_v32i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
ret <32 x i8> %ins31
}
+; build vectors of repeated elements
+
+define <4 x double> @test_buildvector_4f64_2_var(double %a0, double %a1) {
+; AVX-32-LABEL: test_buildvector_4f64_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm0
+; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
+; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_4f64_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT: retq
+ %v0 = insertelement <4 x double> poison, double %a0, i32 0
+ %v1 = insertelement <4 x double> %v0, double %a1, i32 1
+ %v2 = insertelement <4 x double> %v1, double %a1, i32 2
+ %v3 = insertelement <4 x double> %v2, double %a0, i32 3
+ ret <4 x double> %v3
+}
+
+define <4 x double> @test_buildvector_4f64_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_4f64_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-32-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-32-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_4f64_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
+; AVX-64-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
+; AVX-64-NEXT: vmovlhps {{.*#+}} xmm2 = xmm1[0],xmm0[0]
+; AVX-64-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT: retq
+ %a0 = load double, ptr %p0
+ %a1 = load double, ptr %p1
+ %v0 = insertelement <4 x double> poison, double %a0, i32 0
+ %v1 = insertelement <4 x double> %v0, double %a1, i32 1
+ %v2 = insertelement <4 x double> %v1, double %a1, i32 2
+ %v3 = insertelement <4 x double> %v2, double %a0, i32 3
+ ret <4 x double> %v3
+}
+
+define <8 x float> @test_buildvector_8f32_2_var(float %a0, float %a1) {
+; AVX-32-LABEL: test_buildvector_8f32_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm1
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT: retl
+;
+; AVX1-64-LABEL: test_buildvector_8f32_2_var:
+; AVX1-64: # %bb.0:
+; AVX1-64-NEXT: vshufps {{.*#+}} xmm2 = xmm0[0,0,0,3]
+; AVX1-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[0]
+; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX1-64-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0,0]
+; AVX1-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-64-NEXT: retq
+;
+; AVX2-64-LABEL: test_buildvector_8f32_2_var:
+; AVX2-64: # %bb.0:
+; AVX2-64-NEXT: vbroadcastss %xmm0, %xmm0
+; AVX2-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm0[0,1,2],xmm1[0]
+; AVX2-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
+; AVX2-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX2-64-NEXT: retq
+ %v0 = insertelement <8 x float> poison, float %a0, i32 0
+ %v1 = insertelement <8 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <8 x float> %v1, float %a0, i32 2
+ %v3 = insertelement <8 x float> %v2, float %a0, i32 3
+ %v4 = insertelement <8 x float> %v3, float %a0, i32 4
+ %v5 = insertelement <8 x float> %v4, float %a0, i32 5
+ %v6 = insertelement <8 x float> %v5, float %a0, i32 6
+ %v7 = insertelement <8 x float> %v6, float %a1, i32 7
+ ret <8 x float> %v7
+}
+
+define <8 x float> @test_buildvector_8f32_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_8f32_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vbroadcastss (%eax), %xmm1
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_8f32_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; AVX-64-NEXT: vbroadcastss (%rdi), %xmm1
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm1[0,1,2],xmm0[0]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[2,3]
+; AVX-64-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX-64-NEXT: retq
+ %a0 = load float, ptr %p0
+ %a1 = load float, ptr %p1
+ %v0 = insertelement <8 x float> poison, float %a0, i32 0
+ %v1 = insertelement <8 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <8 x float> %v1, float %a0, i32 2
+ %v3 = insertelement <8 x float> %v2, float %a0, i32 3
+ %v4 = insertelement <8 x float> %v3, float %a0, i32 4
+ %v5 = insertelement <8 x float> %v4, float %a0, i32 5
+ %v6 = insertelement <8 x float> %v5, float %a0, i32 6
+ %v7 = insertelement <8 x float> %v6, float %a1, i32 7
+ ret <8 x float> %v7
+}
+
+define <16 x i16> @test_buildvector_16i16_2_var(i16 %a0, i16 %a1) {
+; AVX1-32-LABEL: test_buildvector_16i16_2_var:
+; AVX1-32: # %bb.0:
+; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX1-32-NEXT: vmovd %eax, %xmm0
+; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX1-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vmovd %ecx, %xmm1
+; AVX1-32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $4, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $5, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-32-NEXT: retl
+;
+; AVX1-64-LABEL: test_buildvector_16i16_2_var:
+; AVX1-64: # %bb.0:
+; AVX1-64-NEXT: vmovd %esi, %xmm0
+; AVX1-64-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $2, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $4, %esi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
+; AVX1-64-NEXT: vmovd %edi, %xmm1
+; AVX1-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $2, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $3, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $4, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $5, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $6, %edi, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $7, %esi, %xmm1, %xmm1
+; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-64-NEXT: retq
+;
+; AVX2-32-LABEL: test_buildvector_16i16_2_var:
+; AVX2-32: # %bb.0:
+; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX2-32-NEXT: vmovd %eax, %xmm0
+; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX2-32-NEXT: vpinsrw $1, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $2, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $3, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $4, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $6, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $7, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vmovd %ecx, %xmm1
+; AVX2-32-NEXT: vpinsrw $1, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $4, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $5, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $7, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-32-NEXT: retl
+;
+; AVX2-64-LABEL: test_buildvector_16i16_2_var:
+; AVX2-64: # %bb.0:
+; AVX2-64-NEXT: vmovd %esi, %xmm0
+; AVX2-64-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $2, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $4, %esi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $5, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $6, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $7, %edi, %xmm0, %xmm0
+; AVX2-64-NEXT: vmovd %edi, %xmm1
+; AVX2-64-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $2, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $3, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $4, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $5, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $6, %edi, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $7, %esi, %xmm1, %xmm1
+; AVX2-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-64-NEXT: retq
+ %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0
+ %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1
+ %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2
+ %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3
+ %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4
+ %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5
+ %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6
+ %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7
+ %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8
+ %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9
+ %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10
+ %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11
+ %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12
+ %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13
+ %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14
+ %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15
+ ret <16 x i16> %v15
+}
+
+define <16 x i16> @test_buildvector_16i16_2_load(ptr %p0, ptr %p1) {
+; AVX1-32-LABEL: test_buildvector_16i16_2_load:
+; AVX1-32: # %bb.0:
+; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX1-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX1-32-NEXT: movzwl (%eax), %eax
+; AVX1-32-NEXT: movzwl (%ecx), %ecx
+; AVX1-32-NEXT: vmovd %ecx, %xmm0
+; AVX1-32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX1-32-NEXT: vmovd %eax, %xmm1
+; AVX1-32-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX1-32-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-32-NEXT: retl
+;
+; AVX1-64-LABEL: test_buildvector_16i16_2_load:
+; AVX1-64: # %bb.0:
+; AVX1-64-NEXT: movzwl (%rdi), %eax
+; AVX1-64-NEXT: movzwl (%rsi), %ecx
+; AVX1-64-NEXT: vmovd %ecx, %xmm0
+; AVX1-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX1-64-NEXT: vmovd %eax, %xmm1
+; AVX1-64-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX1-64-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-64-NEXT: retq
+;
+; AVX2-32-LABEL: test_buildvector_16i16_2_load:
+; AVX2-32: # %bb.0:
+; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX2-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX2-32-NEXT: movzwl (%eax), %eax
+; AVX2-32-NEXT: movzwl (%ecx), %ecx
+; AVX2-32-NEXT: vmovd %ecx, %xmm0
+; AVX2-32-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX2-32-NEXT: vmovd %eax, %xmm1
+; AVX2-32-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX2-32-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX2-32-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-32-NEXT: retl
+;
+; AVX2-64-LABEL: test_buildvector_16i16_2_load:
+; AVX2-64: # %bb.0:
+; AVX2-64-NEXT: movzwl (%rdi), %eax
+; AVX2-64-NEXT: movzwl (%rsi), %ecx
+; AVX2-64-NEXT: vmovd %ecx, %xmm0
+; AVX2-64-NEXT: vpinsrw $1, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $2, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $4, %ecx, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $5, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $6, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT: vpinsrw $7, %eax, %xmm0, %xmm0
+; AVX2-64-NEXT: vmovd %eax, %xmm1
+; AVX2-64-NEXT: vpinsrw $1, %ecx, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $2, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $3, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $4, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $6, %eax, %xmm1, %xmm1
+; AVX2-64-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm1
+; AVX2-64-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0
+; AVX2-64-NEXT: retq
+ %a0 = load i16, ptr %p0
+ %a1 = load i16, ptr %p1
+ %v0 = insertelement <16 x i16> poison, i16 %a0, i16 0
+ %v1 = insertelement <16 x i16> %v0, i16 %a1, i16 1
+ %v2 = insertelement <16 x i16> %v1, i16 %a0, i16 2
+ %v3 = insertelement <16 x i16> %v2, i16 %a0, i16 3
+ %v4 = insertelement <16 x i16> %v3, i16 %a0, i16 4
+ %v5 = insertelement <16 x i16> %v4, i16 %a0, i16 5
+ %v6 = insertelement <16 x i16> %v5, i16 %a0, i16 6
+ %v7 = insertelement <16 x i16> %v6, i16 %a1, i16 7
+ %v8 = insertelement <16 x i16> %v7, i16 %a1, i16 8
+ %v9 = insertelement <16 x i16> %v8, i16 %a0, i16 9
+ %v10 = insertelement <16 x i16> %v9, i16 %a1, i16 10
+ %v11 = insertelement <16 x i16> %v10, i16 %a1, i16 11
+ %v12 = insertelement <16 x i16> %v11, i16 %a1, i16 12
+ %v13 = insertelement <16 x i16> %v12, i16 %a0, i16 13
+ %v14 = insertelement <16 x i16> %v13, i16 %a0, i16 14
+ %v15 = insertelement <16 x i16> %v14, i16 %a0, i16 15
+ ret <16 x i16> %v15
+}
+
; PR30780
define <8 x i32> @test_buildvector_v8i32_splat_sext_i8(i8 %in) {
@@ -485,3 +832,4 @@ define <8 x i32> @test_buildvector_v8i32_splat_zext_i8(i8 %in) {
%splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
ret <8 x i32> %splat
}
+
diff --git a/llvm/test/CodeGen/X86/build-vector-512.ll b/llvm/test/CodeGen/X86/build-vector-512.ll
index ac33ac96db416..5d38f087aa1b3 100644
--- a/llvm/test/CodeGen/X86/build-vector-512.ll
+++ b/llvm/test/CodeGen/X86/build-vector-512.ll
@@ -476,3 +476,164 @@ define <64 x i8> @test_buildvector_v64i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
%ins63 = insertelement <64 x i8> %ins62, i8 %a63, i32 63
ret <64 x i8> %ins63
}
+
+; build vectors of repeated elements
+
+define <8 x double> @test_buildvector_8f64_2_var(double %a0, double %a1) {
+; AVX-32-LABEL: test_buildvector_8f64_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-32-NEXT: vmovups {{[0-9]+}}(%esp), %xmm1
+; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-32-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_8f64_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
+; AVX-64-NEXT: vmovlhps {{.*#+}} xmm1 = xmm0[0],xmm1[0]
+; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-64-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-64-NEXT: retq
+ %v0 = insertelement <8 x double> poison, double %a0, i32 0
+ %v1 = insertelement <8 x double> %v0, double %a1, i32 1
+ %v2 = insertelement <8 x double> %v1, double %a0, i32 2
+ %v3 = insertelement <8 x double> %v2, double %a0, i32 3
+ %v4 = insertelement <8 x double> %v3, double %a0, i32 4
+ %v5 = insertelement <8 x double> %v4, double %a0, i32 5
+ %v6 = insertelement <8 x double> %v5, double %a0, i32 6
+ %v7 = insertelement <8 x double> %v6, double %a1, i32 7
+ ret <8 x double> %v7
+}
+
+define <8 x double> @test_buildvector_8f64_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_8f64_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm0[0,1],mem[0,1]
+; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-32-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-32-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_8f64_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vmovddup {{.*#+}} xmm0 = mem[0,0]
+; AVX-64-NEXT: vmovhps {{.*#+}} xmm1 = xmm0[0,1],mem[0,1]
+; AVX-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm2
+; AVX-64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX-64-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX-64-NEXT: retq
+ %a0 = load double, ptr %p0
+ %a1 = load double, ptr %p1
+ %v0 = insertelement <8 x double> poison, double %a0, i32 0
+ %v1 = insertelement <8 x double> %v0, double %a1, i32 1
+ %v2 = insertelement <8 x double> %v1, double %a0, i32 2
+ %v3 = insertelement <8 x double> %v2, double %a0, i32 3
+ %v4 = insertelement <8 x double> %v3, double %a0, i32 4
+ %v5 = insertelement <8 x double> %v4, double %a0, i32 5
+ %v6 = insertelement <8 x double> %v5, double %a0, i32 6
+ %v7 = insertelement <8 x double> %v6, double %a1, i32 7
+ ret <8 x double> %v7
+}
+
+define <16 x float> @test_buildvector_16f32_2_var(float %a0, float %a1) {
+; AVX-32-LABEL: test_buildvector_16f32_2_var:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0
+; AVX-32-NEXT: vpmovsxbd {{.*#+}} xmm1 = [0,17,0,0]
+; AVX-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vpermi2ps %zmm0, %zmm2, %zmm1
+; AVX-32-NEXT: vblendps {{.*#+}} xmm3 = xmm2[0],xmm0[1,2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm2[0]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-32-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_16f32_2_var:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
+; AVX-64-NEXT: vpmovsxbd {{.*#+}} xmm2 = [0,16,0,0]
+; AVX-64-NEXT: vbroadcastss %xmm0, %xmm0
+; AVX-64-NEXT: vpermi2ps %zmm1, %zmm0, %zmm2
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm0[0,1,2],xmm1[0]
+; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX-64-NEXT: vpmovsxbd {{.*#+}} ymm3 = [0,16,0,0,0,17,18,19]
+; AVX-64-NEXT: vpermi2ps %zmm0, %zmm1, %zmm3
+; AVX-64-NEXT: vinsertf64x4 $1, %ymm3, %zmm2, %zmm0
+; AVX-64-NEXT: retq
+ %v0 = insertelement <16 x float> poison, float %a0, i32 0
+ %v1 = insertelement <16 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <16 x float> %v1, float %a0, i32 2
+ %v3 = insertelement <16 x float> %v2, float %a0, i32 3
+ %v4 = insertelement <16 x float> %v3, float %a0, i32 4
+ %v5 = insertelement <16 x float> %v4, float %a0, i32 5
+ %v6 = insertelement <16 x float> %v5, float %a0, i32 6
+ %v7 = insertelement <16 x float> %v6, float %a1, i32 7
+ %v8 = insertelement <16 x float> %v7, float %a1, i32 8
+ %v9 = insertelement <16 x float> %v8, float %a0, i32 9
+ %v10 = insertelement <16 x float> %v9, float %a1, i32 10
+ %v11 = insertelement <16 x float> %v10, float %a1, i32 11
+ %v12 = insertelement <16 x float> %v11, float %a1, i32 12
+ %v13 = insertelement <16 x float> %v12, float %a0, i32 13
+ %v14 = insertelement <16 x float> %v13, float %a0, i32 14
+ %v15 = insertelement <16 x float> %v14, float %a0, i32 15
+ ret <16 x float> %v15
+}
+
+define <16 x float> @test_buildvector_16f32_2_load(ptr %p0, ptr %p1) {
+; AVX-32-LABEL: test_buildvector_16f32_2_load:
+; AVX-32: # %bb.0:
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; AVX-32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; AVX-32-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]
+; AVX-32-NEXT: vbroadcastss (%ecx), %xmm1
+; AVX-32-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-32-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0
+; AVX-32-NEXT: vblendps {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]
+; AVX-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
+; AVX-32-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-32-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; AVX-32-NEXT: retl
+;
+; AVX-64-LABEL: test_buildvector_16f32_2_load:
+; AVX-64: # %bb.0:
+; AVX-64-NEXT: vpmovsxbd {{.*#+}} xmm0 = [0,17,0,0]
+; AVX-64-NEXT: vbroadcastss (%rdi), %xmm1
+; AVX-64-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; AVX-64-NEXT: vpermi2ps %zmm1, %zmm2, %zmm0
+; AVX-64-NEXT: vblendps {{.*#+}} xmm3 = xmm2[0],xmm1[1,2,3]
+; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],xmm2[0]
+; AVX-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[2,3]
+; AVX-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX-64-NEXT: vinsertf64x4 $1, %ymm0, %zmm1, %zmm0
+; AVX-64-NEXT: retq
+ %a0 = load float, ptr %p0
+ %a1 = load float, ptr %p1
+ %v0 = insertelement <16 x float> poison, float %a0, i32 0
+ %v1 = insertelement <16 x float> %v0, float %a1, i32 1
+ %v2 = insertelement <16 x float> %v1, float %a0, i32 2
+ %v3 = insertelement <16 x float> %v2, float %a0, i32 3
+ %v4 = insertelement <16 x float> %v3, float %a0, i32 4
+ %v5 = insertelement <16 x float> %v4, float %a0, i32 5
+ %v6 = insertelement <16 x float> %v5, float %a0, i32 6
+ %v7 = insertelement <16 x float> %v6, float %a1, i32 7
+ %v8 = insertelement <16 x float> %v7, float %a1, i32 8
+ %v9 = insertelement <16 x float> %v8, float %a0, i32 9
+ %v10 = insertelement <16 x float> %v9, float %a1, i32 10
+ %v11 = insertelement <16 x float> %v10, float %a1, i32 11
+ %v12 = insertelement <16 x float> %v11, float %a1, i32 12
+ %v13 = insertelement <16 x float> %v12, float %a0, i32 13
+ %v14 = insertelement <16 x float> %v13, float %a0, i32 14
+ %v15 = insertelement <16 x float> %v14, float %a0, i32 15
+ ret <16 x float> %v15
+}
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