[llvm] [RISCV] Add ISel patterns for Xqcia instructions (PR #136548)

[Craig Topper via llvm-commits]

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@@ -422,6 +422,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   else if (!Subtarget.hasVendorXTHeadCondMov())
     setOperationAction(ISD::SELECT, XLenVT, Custom);
 
+  if (Subtarget.hasVendorXqcia()) {
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topperc wrote:

Can we add `!Subtarget.is64Bit()` here to be consistent with the isel patterns?

https://github.com/llvm/llvm-project/pull/136548