[llvm] [ms] [llvm-ml] Allow PTR casting of registers to their own size (PR #132751)

[Phoebe Wang via llvm-commits]

================
@@ -2577,14 +2584,36 @@ bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
   return false;
 }
 
+uint16_t RegSizeInBits(const MCRegisterInfo &MRI, MCRegister RegNo) {
+  if (X86MCRegisterClasses[X86::GR8RegClassID].contains(RegNo))
+    return 8;
+  if (X86MCRegisterClasses[X86::GR16RegClassID].contains(RegNo))
+    return 16;
+  if (X86MCRegisterClasses[X86::GR32RegClassID].contains(RegNo))
+    return 32;
+  if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
+    return 64;
+  if (X86MCRegisterClasses[X86::RFP80RegClassID].contains(RegNo))
+    return 80;
+  if (X86MCRegisterClasses[X86::VR128RegClassID].contains(RegNo) ||
+      X86MCRegisterClasses[X86::VR128XRegClassID].contains(RegNo))
----------------
phoebewang wrote:

XMM is the biggest trouble since you can't tell it's a scalar FP or vector. However, YMM/ZMM have size problem in some instructions too, e.g.,

```
vcvtpd2ps ymm0, zmmptr rax
vcvtps2pd zmm0, ymmptr rax
```

OTOH, I don't see a size mismatch in GPR instructions so far. So would be good to limit to GPR only.

https://github.com/llvm/llvm-project/pull/132751