[llvm] AMDGPU: Fix the double rounding issue in v2f64 -> v2f16 conversion (PR #135659)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 21 04:20:27 PDT 2025
================
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SAFE-SDAG %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 < %s | FileCheck -check-prefixes=GFX950,GFX950-SAFE-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GFX950,GFX950-UNSAFE %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx950 -global-isel=0 -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GFX950,GFX950-UNSAFE %s
+
+define <2 x half> @v_test_cvt_v2f32_v2f16(<2 x float> %src) {
+; GFX950-LABEL: v_test_cvt_v2f32_v2f16:
+; GFX950: ; %bb.0:
+; GFX950-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
+; GFX950-NEXT: s_setpc_b64 s[30:31]
+ %res = fptrunc <2 x float> %src to <2 x half>
+ ret <2 x half> %res
+}
+
+define <2 x half> @v_test_cvt_v2f64_v2f16(<2 x double> %src) {
+; GFX950-SAFE-SDAG-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-SAFE-SDAG: ; %bb.0:
+; GFX950-SAFE-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-SDAG-NEXT: s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX950-SAFE-SDAG-NEXT: s_movk_i32 s1, 0xffe
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_bfe_u32 v5, v1, 20, 11
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v0, v4, s1, v0
+; GFX950-SAFE-SDAG-NEXT: v_sub_u32_e32 v6, 0x3f1, v5
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX950-SAFE-SDAG-NEXT: v_med3_i32 v6, v6, 0, 13
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v7, v6, v4
+; GFX950-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
+; GFX950-SAFE-SDAG-NEXT: v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SAFE-SDAG-NEXT: v_lshl_or_b32 v6, v5, 12, v0
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX950-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SAFE-SDAG-NEXT: s_movk_i32 s2, 0x40f
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-SDAG-NEXT: v_and_b32_e32 v6, 7, v4
+; GFX950-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SAFE-SDAG-NEXT: s_mov_b32 s3, 0x8000
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX950-SAFE-SDAG-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX950-SAFE-SDAG-NEXT: v_mov_b32_e32 v6, 0x7c00
+; GFX950-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
+; GFX950-SAFE-SDAG-NEXT: v_mov_b32_e32 v7, 0x7e00
+; GFX950-SAFE-SDAG-NEXT: s_nop 0
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s2, v5
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-SDAG-NEXT: v_bfe_u32 v4, v3, 20, 11
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-SDAG-NEXT: v_sub_u32_e32 v5, 0x3f1, v4
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-SDAG-NEXT: v_med3_i32 v5, v5, 0, 13
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v8, v5, v2
+; GFX950-SAFE-SDAG-NEXT: v_lshlrev_b32_e32 v5, v5, v8
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
+; GFX950-SAFE-SDAG-NEXT: v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SAFE-SDAG-NEXT: v_lshl_or_b32 v5, v4, 12, v1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v2, v8, v2
+; GFX950-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SAFE-SDAG-NEXT: s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-SDAG-NEXT: s_nop 0
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-SAFE-SDAG-NEXT: v_and_b32_e32 v5, 7, v2
+; GFX950-SAFE-SDAG-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-SDAG-NEXT: s_nop 0
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_or_b32_e32 v5, v5, v8
+; GFX950-SAFE-SDAG-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX950-SAFE-SDAG-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc
+; GFX950-SAFE-SDAG-NEXT: v_cmp_eq_u32_e32 vcc, s2, v4
+; GFX950-SAFE-SDAG-NEXT: s_nop 1
+; GFX950-SAFE-SDAG-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-SDAG-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-SDAG-NEXT: v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-SDAG-NEXT: v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-SAFE-GISEL-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-SAFE-GISEL: ; %bb.0:
+; GFX950-SAFE-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SAFE-GISEL-NEXT: s_movk_i32 s0, 0x1ff
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v0, v1, s0, v0
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v4, 8, v1
+; GFX950-SAFE-GISEL-NEXT: s_movk_i32 s1, 0xffe
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_bfe_u32 v5, v1, 20, 11
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v0, v4, s1, v0
+; GFX950-SAFE-GISEL-NEXT: v_sub_u32_e32 v6, 0x3f1, v5
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v4, 0x1000, v0
+; GFX950-SAFE-GISEL-NEXT: v_med3_i32 v6, v6, 0, 13
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v7, v6, v4
+; GFX950-SAFE-GISEL-NEXT: v_lshlrev_b32_e32 v6, v6, v7
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, v6, v4
+; GFX950-SAFE-GISEL-NEXT: v_add_u32_e32 v5, 0xfffffc10, v5
+; GFX950-SAFE-GISEL-NEXT: v_lshl_or_b32 v6, v5, 12, v0
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX950-SAFE-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
+; GFX950-SAFE-GISEL-NEXT: s_movk_i32 s2, 0x40f
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-GISEL-NEXT: v_and_b32_e32 v6, 7, v4
+; GFX950-SAFE-GISEL-NEXT: v_cmp_lt_i32_e32 vcc, 5, v6
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v4, 2, v4
+; GFX950-SAFE-GISEL-NEXT: s_mov_b32 s3, 0x8000
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v6
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX950-SAFE-GISEL-NEXT: v_add_u32_e32 v4, v4, v6
+; GFX950-SAFE-GISEL-NEXT: v_mov_b32_e32 v6, 0x7c00
+; GFX950-SAFE-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 31, v5
+; GFX950-SAFE-GISEL-NEXT: v_mov_b32_e32 v7, 0x7e00
+; GFX950-SAFE-GISEL-NEXT: s_nop 0
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v7, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s2, v5
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v1, v3, s0, v2
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v2, 8, v3
+; GFX950-SAFE-GISEL-NEXT: v_bfe_u32 v4, v3, 20, 11
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v1, v2, s1, v1
+; GFX950-SAFE-GISEL-NEXT: v_sub_u32_e32 v5, 0x3f1, v4
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v2, 0x1000, v1
+; GFX950-SAFE-GISEL-NEXT: v_med3_i32 v5, v5, 0, 13
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v8, v5, v2
+; GFX950-SAFE-GISEL-NEXT: v_lshlrev_b32_e32 v5, v5, v8
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
+; GFX950-SAFE-GISEL-NEXT: v_add_u32_e32 v4, 0xfffffc10, v4
+; GFX950-SAFE-GISEL-NEXT: v_lshl_or_b32 v5, v4, 12, v1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v2, v8, v2
+; GFX950-SAFE-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 1, v4
+; GFX950-SAFE-GISEL-NEXT: s_mov_b32 s0, 0x5040100
+; GFX950-SAFE-GISEL-NEXT: s_nop 0
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
+; GFX950-SAFE-GISEL-NEXT: v_and_b32_e32 v5, 7, v2
+; GFX950-SAFE-GISEL-NEXT: v_cmp_lt_i32_e32 vcc, 5, v5
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; GFX950-SAFE-GISEL-NEXT: s_nop 0
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 3, v5
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_or_b32_e32 v5, v5, v8
+; GFX950-SAFE-GISEL-NEXT: v_add_u32_e32 v2, v2, v5
+; GFX950-SAFE-GISEL-NEXT: v_cmp_gt_i32_e32 vcc, 31, v4
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v7, vcc
+; GFX950-SAFE-GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s2, v4
+; GFX950-SAFE-GISEL-NEXT: s_nop 1
+; GFX950-SAFE-GISEL-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; GFX950-SAFE-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
+; GFX950-SAFE-GISEL-NEXT: v_and_or_b32 v1, v2, s3, v1
+; GFX950-SAFE-GISEL-NEXT: v_perm_b32 v0, v1, v0, s0
+; GFX950-SAFE-GISEL-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-UNSAFE-LABEL: v_test_cvt_v2f64_v2f16:
+; GFX950-UNSAFE: ; %bb.0:
+; GFX950-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-UNSAFE-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
+; GFX950-UNSAFE-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
+; GFX950-UNSAFE-NEXT: v_cvt_f16_f32_e32 v0, v0
+; GFX950-UNSAFE-NEXT: v_cvt_f16_f32_e32 v1, v1
+; GFX950-UNSAFE-NEXT: s_mov_b32 s0, 0x5040100
+; GFX950-UNSAFE-NEXT: v_perm_b32 v0, v1, v0, s0
+; GFX950-UNSAFE-NEXT: s_setpc_b64 s[30:31]
+ %res = fptrunc <2 x double> %src to <2 x half>
+ ret <2 x half> %res
+}
+
----------------
arsenm wrote:
Should also add tests with fast math flags instead of the global options
https://github.com/llvm/llvm-project/pull/135659
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