[llvm] Attributor: Add noalias.addrspace attribute for store and load (PR #136553)

[Matt Arsenault via llvm-commits]

================
@@ -0,0 +1,87 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s
+
+define amdgpu_kernel void @no_alias_addr_space_select(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, ptr addrspace(5) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {
+; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_select(
+; CHECK-SAME: ptr addrspace(1) [[GPTR:%.*]], ptr addrspace(3) [[LPTR:%.*]], ptr addrspace(5) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[A:%.*]] = addrspacecast ptr addrspace(1) [[GPTR]] to ptr
+; CHECK-NEXT:    [[B:%.*]] = addrspacecast ptr addrspace(3) [[LPTR]] to ptr
+; CHECK-NEXT:    [[C:%.*]] = addrspacecast ptr addrspace(5) [[SPTR]] to ptr
+; CHECK-NEXT:    [[ADD_A:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 [[OFFSET]]
+; CHECK-NEXT:    [[PTR:%.*]] = select i1 [[COND1]], ptr [[ADD_A]], ptr [[B]]
+; CHECK-NEXT:    [[PTR2:%.*]] = select i1 [[COND2]], ptr [[PTR]], ptr [[C]]
+; CHECK-NEXT:    store i32 [[VAL]], ptr [[PTR2]], align 4, !noalias.addrspace [[META0:![0-9]+]]
+; CHECK-NEXT:    ret void
+;
+  %a = addrspacecast ptr addrspace(1) %gptr to ptr
+  %b = addrspacecast ptr addrspace(3) %lptr to ptr
+  %c = addrspacecast ptr addrspace(5) %sptr to ptr
+  %add_a = getelementptr inbounds i8, ptr %a, i32 %offset
+  %ptr = select i1 %cond1, ptr %add_a, ptr %b
+  %ptr2 = select i1 %cond2, ptr %ptr, ptr %c
+  store i32 %val, ptr %ptr2
+  ret void
+}
+
+define amdgpu_kernel void @no_alias_addr_space_arg(ptr %gptr, i32 %val, i1 %cond) #0 {
+; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_arg(
+; CHECK-SAME: ptr [[GPTR:%.*]], i32 [[VAL:%.*]], i1 [[COND:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    store i32 [[VAL]], ptr [[GPTR]], align 4, !noalias.addrspace [[META1:![0-9]+]]
+; CHECK-NEXT:    ret void
+;
+  %a = addrspacecast ptr %gptr to ptr addrspace(5)
+  %b = addrspacecast ptr %gptr to ptr addrspace(7)
+  %ptr_a = addrspacecast ptr addrspace(5) %a to ptr
+  %ptr_b = addrspacecast ptr addrspace(7) %b to ptr
+  %ptr = select i1 %cond, ptr %ptr_a, ptr %ptr_b
+  store i32 %val, ptr %ptr
+  ret void
+}
+
+define amdgpu_kernel void @no_alias_addr_space_branch(ptr addrspace(1) %gptr, ptr addrspace(3) %lptr, ptr addrspace(5) %sptr, i1 %cond1, i1 %cond2, i32 %val, i32 %offset) #0 {
+; CHECK-LABEL: define amdgpu_kernel void @no_alias_addr_space_branch(
+; CHECK-SAME: ptr addrspace(1) [[GPTR:%.*]], ptr addrspace(3) [[LPTR:%.*]], ptr addrspace(5) [[SPTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]], i32 [[VAL:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    br i1 [[COND1]], label %[[BB_1_TRUE:.*]], label %[[BB_1_FALSE:.*]]
+; CHECK:       [[BB_1_TRUE]]:
+; CHECK-NEXT:    [[A:%.*]] = addrspacecast ptr addrspace(1) [[GPTR]] to ptr
+; CHECK-NEXT:    br label %[[BB_1_END:.*]]
+; CHECK:       [[BB_1_FALSE]]:
+; CHECK-NEXT:    [[B:%.*]] = addrspacecast ptr addrspace(3) [[LPTR]] to ptr
+; CHECK-NEXT:    br label %[[BB_1_END]]
+; CHECK:       [[BB_1_END]]:
+; CHECK-NEXT:    [[PTR1:%.*]] = phi ptr [ [[A]], %[[BB_1_TRUE]] ], [ [[B]], %[[BB_1_FALSE]] ]
+; CHECK-NEXT:    br i1 [[COND2]], label %[[BB_2_TRUE:.*]], label %[[BB_2_END:.*]]
+; CHECK:       [[BB_2_TRUE]]:
+; CHECK-NEXT:    [[C:%.*]] = addrspacecast ptr addrspace(5) [[SPTR]] to ptr
+; CHECK-NEXT:    br label %[[BB_2_END]]
+; CHECK:       [[BB_2_END]]:
+; CHECK-NEXT:    [[PTR2:%.*]] = phi ptr [ [[PTR1]], %[[BB_1_END]] ], [ [[C]], %[[BB_2_TRUE]] ]
+; CHECK-NEXT:    store i32 [[VAL]], ptr [[PTR2]], align 4, !noalias.addrspace [[META0]]
+; CHECK-NEXT:    ret void
+;
+  br i1 %cond1, label %bb.1.true, label %bb.1.false
+bb.1.true:
+  %a = addrspacecast ptr addrspace(1) %gptr to ptr
+  br label %bb.1.end
+
+bb.1.false:
+  %b = addrspacecast ptr addrspace(3) %lptr to ptr
+  br label %bb.1.end
+
+bb.1.end:
+  %ptr1 = phi ptr [ %a, %bb.1.true ], [ %b, %bb.1.false ]
+  br i1 %cond2, label %bb.2.true, label %bb.2.end
+
+bb.2.true:
+  %c = addrspacecast ptr addrspace(5) %sptr to ptr
+  br label %bb.2.end
+
+bb.2.end:
+  %ptr2 = phi ptr [ %ptr1, %bb.1.end ], [ %c, %bb.2.true ]
+  store i32 %val, ptr %ptr2
+  ret void
+}
+;.
----------------
arsenm wrote:

Test atomicrmw, cmpxchg, and some memory intrinsics 

https://github.com/llvm/llvm-project/pull/136553