[llvm] [RISCV] Remove `AND` mask generated by `( zext ( atomic_load ) )` by replacing the load with `zextload` for orderings not stronger then monotonic. (PR #136502)

[Jan Górski via llvm-commits]

janagor wrote:

For _testing purposes only_ I reverted the changes from this patch and made such change:
```
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 53244a990a86..bb247574a5f2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -386,6 +386,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
     switch (TLI.getExtendForAtomicOps()) {
     case ISD::SIGN_EXTEND:
       ExtType = ISD::SEXTLOAD;
+      ExtType = ISD::ZEXTLOAD;
       break;
     case ISD::ZERO_EXTEND:
       ExtType = ISD::ZEXTLOAD;
```
just to check what is generated for a following snippet (the code from original [issue](https://github.com/llvm/llvm-project/issues/131476)):
```c
#include <stdbool.h>
extern bool t1;
bool test1(void) {
    return __atomic_load_n(&t1, __ATOMIC_RELAXED);
}
```
I run:
```bash
./bin/clang --target=riscv64 -O1 -S -emit-llvm atomic-ops-load.c -o test.ll
./bin/llc -filetype=asm test.ll -o test.s -O1 -mtriple=riscv64 --print-after-isel -debug 2> result.txt
```
I got following instructions:
```
test1:                                  # @test1
# %bb.0:                                # %entry
        lui     a0, %hi(t1)
        lb      a0, %lo(t1)(a0)
        ret
.Lfunc_end0:
```
with debug file info that I attached to this comment: [result.txt](https://github.com/user-attachments/files/19862687/result.txt). I think the main thing from it is the following info:
```
ISEL: Starting selection on root node: t9: i64,ch = AtomicLoad<(dereferenceable load monotonic (s8) from @t1), zext from i8> t0, t15
ISEL: Starting pattern match
  Initial Opcode index to 1152977
  TypeSwitch[i64] from 1152986 to 1152989
  Morphed node: t9: i64,ch = LB<Mem:(dereferenceable load monotonic (s8) from @t1)> t14, TargetGlobalAddress:i64<ptr @t1> 0 [TF=3], t0
ISEL: Match complete!
```

It seems to me that changing extention type of ISD::ATOMIC_LOAD is not enough. Does this imply that there should be a match for `(zext(atomic_load))` in tablegen that would catch this pattern?





https://github.com/llvm/llvm-project/pull/136502