[llvm] [TableGen][RISCV][AArch64] Properly implement isAnyExtLoad/isSignExtLoad/isZeroExtLoad for IsAtomic in SelectionDAG. (PR #137096)

Sergei Barannikov via llvm-commits llvm-commits at lists.llvm.org
Wed Apr 23 22:30:36 PDT 2025 

https://github.com/s-barannikov commented:

The title should mention GISel?


https://github.com/llvm/llvm-project/pull/137096

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