[clang] [llvm] [RISCV] Add Andes N45/NX45 processor definition (PR #136670)

[Jim Lin via llvm-commits]

================
@@ -625,3 +625,33 @@ def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
                                           FeatureStdExtZbkb,
                                           FeatureStdExtZcb,
                                           FeatureStdExtZcmp]>;
+
+def ANDES_N45 : RISCVProcessorModel<"andes-n45",
+                                    NoSchedModel,
+                                    [Feature32Bit,
+                                     FeatureStdExtI,
+                                     FeatureStdExtZicsr,
+                                     FeatureStdExtZifencei,
+                                     FeatureStdExtM,
+                                     FeatureStdExtA,
+                                     FeatureStdExtF,
+                                     FeatureStdExtD,
+                                     FeatureStdExtC,
+                                     FeatureStdExtZba,
+                                     FeatureStdExtZbb,
+                                     FeatureStdExtZbs]>;
+
+def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
+                                     NoSchedModel,
+                                     [Feature64Bit,
+                                      FeatureStdExtI,
+                                      FeatureStdExtZicsr,
+                                      FeatureStdExtZifencei,
+                                      FeatureStdExtM,
+                                      FeatureStdExtA,
+                                      FeatureStdExtF,
+                                      FeatureStdExtD,
+                                      FeatureStdExtC,
+                                      FeatureStdExtZba,
+                                      FeatureStdExtZbb,
+                                      FeatureStdExtZbs]>;
----------------
tclin914 wrote:

Done.

https://github.com/llvm/llvm-project/pull/136670