[llvm] 194da37 - [Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation (#135768)

[via llvm-commits]

Author: yingopq
Date: 2025-04-25T17:36:27+08:00
New Revision: 194da37b71a07f9959623231a5fa9fd1b11187cd

URL: https://github.com/llvm/llvm-project/commit/194da37b71a07f9959623231a5fa9fd1b11187cd
DIFF: https://github.com/llvm/llvm-project/commit/194da37b71a07f9959623231a5fa9fd1b11187cd.diff

LOG: [Mips] Do not emit instruction teq if divisor is non-zero immediate value in FastISel implementation (#135768)

Add a check before emitting the teq instruction to check whether the
divisor is a non-zero immediate value.

Fix #130629.

Added: 
    llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll

Modified: 
    llvm/lib/Target/Mips/MipsFastISel.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index ec138fb3f1906..f3812d185ec92 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1947,7 +1947,10 @@ bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
     return false;
 
   emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
-  emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+  if (!isa<ConstantInt>(I->getOperand(1)) ||
+      dyn_cast<ConstantInt>(I->getOperand(1))->isZero()) {
+    emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
+  }
 
   Register ResultReg = createResultReg(&Mips::GPR32RegClass);
   if (!ResultReg)

diff  --git a/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll
new file mode 100644
index 0000000000000..7c09c49a8c374
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/div-imm.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic | FileCheck %s
+
+define i32 @div_imm_non_zero(i32 signext %a) nounwind {
+; CHECK-LABEL: div_imm_non_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $1, $zero, 1234
+; CHECK-NEXT:    div $zero, $4, $1
+; CHECK-NEXT:    mflo $2
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    nop
+entry:
+  %div = sdiv i32 %a, 1234
+  ret i32 %div
+}
+
+define i32 @div_imm_zero(i32 signext %a) nounwind {
+; CHECK-LABEL: div_imm_zero:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addiu $1, $zero, 0
+; CHECK-NEXT:    div $zero, $4, $zero
+; CHECK-NEXT:    teq $zero, $zero, 7
+; CHECK-NEXT:    mflo $2
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    nop
+entry:
+  %div = sdiv i32 %a, 0
+  ret i32 %div
+}