[llvm] [CodeGen] Use `TRI::regunits()` (NFC) (PR #137356)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-regalloc

Author: Sergei Barannikov (s-barannikov)

<details>
<summary>Changes</summary>



---
Full diff: https://github.com/llvm/llvm-project/pull/137356.diff


2 Files Affected:

- (modified) llvm/include/llvm/CodeGen/RegisterClassInfo.h (+2-2) 
- (modified) llvm/lib/CodeGen/MachineLICM.cpp (+19-19) 


``````````diff
diff --git a/llvm/include/llvm/CodeGen/RegisterClassInfo.h b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
index 800bebea0dddb..99beae761c40b 100644
--- a/llvm/include/llvm/CodeGen/RegisterClassInfo.h
+++ b/llvm/include/llvm/CodeGen/RegisterClassInfo.h
@@ -117,8 +117,8 @@ class RegisterClassInfo {
   /// CalleeSavedAliases.
   MCRegister getLastCalleeSavedAlias(MCRegister PhysReg) const {
     MCRegister CSR;
-    for (MCRegUnitIterator UI(PhysReg, TRI); UI.isValid(); ++UI) {
-      CSR = CalleeSavedAliases[*UI];
+    for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
+      CSR = CalleeSavedAliases[Unit];
       if (CSR)
         break;
     }
diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp
index d13d41c3da20b..4b3eefe33ac2c 100644
--- a/llvm/lib/CodeGen/MachineLICM.cpp
+++ b/llvm/lib/CodeGen/MachineLICM.cpp
@@ -495,8 +495,8 @@ static void applyBitsNotInRegMaskToRegUnitsMask(const TargetRegisterInfo &TRI,
         break;
 
       if (PhysReg && !((Word >> Bit) & 1)) {
-        for (MCRegUnitIterator RUI(PhysReg, &TRI); RUI.isValid(); ++RUI)
-          RUsFromRegsNotInMask.set(*RUI);
+        for (MCRegUnit Unit : TRI.regunits(PhysReg))
+          RUsFromRegsNotInMask.set(Unit);
       }
     }
   }
@@ -542,10 +542,10 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
 
     if (!MO.isDef()) {
       if (!HasNonInvariantUse) {
-        for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
+        for (MCRegUnit Unit : TRI->regunits(Reg)) {
           // If it's using a non-loop-invariant register, then it's obviously
           // not safe to hoist.
-          if (RUDefs.test(*RUI) || RUClobbers.test(*RUI)) {
+          if (RUDefs.test(Unit) || RUClobbers.test(Unit)) {
             HasNonInvariantUse = true;
             break;
           }
@@ -555,8 +555,8 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
     }
 
     if (MO.isImplicit()) {
-      for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
-        RUClobbers.set(*RUI);
+      for (MCRegUnit Unit : TRI->regunits(Reg))
+        RUClobbers.set(Unit);
       if (!MO.isDead())
         // Non-dead implicit def? This cannot be hoisted.
         RuledOut = true;
@@ -575,17 +575,17 @@ void MachineLICMImpl::ProcessMI(MachineInstr *MI, BitVector &RUDefs,
     // If we have already seen another instruction that defines the same
     // register, then this is not safe.  Two defs is indicated by setting a
     // PhysRegClobbers bit.
-    for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
-      if (RUDefs.test(*RUI)) {
-        RUClobbers.set(*RUI);
+    for (MCRegUnit Unit : TRI->regunits(Reg)) {
+      if (RUDefs.test(Unit)) {
+        RUClobbers.set(Unit);
         RuledOut = true;
-      } else if (RUClobbers.test(*RUI)) {
+      } else if (RUClobbers.test(Unit)) {
         // MI defined register is seen defined by another instruction in
         // the loop, it cannot be a LICM candidate.
         RuledOut = true;
       }
 
-      RUDefs.set(*RUI);
+      RUDefs.set(Unit);
     }
   }
 
@@ -625,8 +625,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
     // FIXME: That means a reload that're reused in successor block(s) will not
     // be LICM'ed.
     for (const auto &LI : BB->liveins()) {
-      for (MCRegUnitIterator RUI(LI.PhysReg, TRI); RUI.isValid(); ++RUI)
-        RUDefs.set(*RUI);
+      for (MCRegUnit Unit : TRI->regunits(LI.PhysReg))
+        RUDefs.set(Unit);
     }
 
     // Funclet entry blocks will clobber all registers
@@ -648,8 +648,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
       Register Reg = MO.getReg();
       if (!Reg)
         continue;
-      for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
-        TermRUs.set(*RUI);
+      for (MCRegUnit Unit : TRI->regunits(Reg))
+        TermRUs.set(Unit);
     }
   }
 
@@ -668,8 +668,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
 
     Register Def = Candidate.Def;
     bool Safe = true;
-    for (MCRegUnitIterator RUI(Def, TRI); RUI.isValid(); ++RUI) {
-      if (RUClobbers.test(*RUI) || TermRUs.test(*RUI)) {
+    for (MCRegUnit Unit : TRI->regunits(Def)) {
+      if (RUClobbers.test(Unit) || TermRUs.test(Unit)) {
         Safe = false;
         break;
       }
@@ -682,8 +682,8 @@ void MachineLICMImpl::HoistRegionPostRA(MachineLoop *CurLoop) {
     for (const MachineOperand &MO : MI->all_uses()) {
       if (!MO.getReg())
         continue;
-      for (MCRegUnitIterator RUI(MO.getReg(), TRI); RUI.isValid(); ++RUI) {
-        if (RUDefs.test(*RUI) || RUClobbers.test(*RUI)) {
+      for (MCRegUnit Unit : TRI->regunits(MO.getReg())) {
+        if (RUDefs.test(Unit) || RUClobbers.test(Unit)) {
           // If it's using a non-loop-invariant register, then it's obviously
           // not safe to hoist.
           Safe = false;

``````````

</details>


https://github.com/llvm/llvm-project/pull/137356