[llvm] [RISCV] Remove `AND` mask generated by `( zext ( atomic_load ) )` by replacing the load with `zextload` for orderings not stronger then monotonic. (PR #136502)

[Craig Topper via llvm-commits]

Jan =?utf-8?q?Górski?= <jan.a.gorski at wp.pl>,
Jan =?utf-8?q?Górski?= <jan.a.gorski at wp.pl>,
Jan =?utf-8?q?Górski?= <jan.a.gorski at wp.pl>,
Jan =?utf-8?q?Górski?= <jan.a.gorski at wp.pl>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/136502 at github.com>


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@@ -15280,6 +15280,40 @@ static SDValue reverseZExtICmpCombine(SDNode *N, SelectionDAG &DAG,
   return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
 }
 
+static SDValue reduceANDOfAtomicLoad(SDNode *N,
+                                     TargetLowering::DAGCombinerInfo &DCI) {
+  SelectionDAG &DAG = DCI.DAG;
+  if (N->getOpcode() != ISD::AND)
+    return SDValue();
+
+  SDValue N0 = N->getOperand(0);
+  if (N0.getOpcode() != ISD::ATOMIC_LOAD)
+    return SDValue();
+  if (!N0.hasOneUse())
+    return SDValue();
+
+  AtomicSDNode *ALoad = cast<AtomicSDNode>(N0.getNode());
+  if (isStrongerThanMonotonic(ALoad->getSuccessOrdering()))
+    return SDValue();
+
+  EVT LoadedVT = ALoad->getMemoryVT();
+  uint64_t Mask = maskTrailingOnes<uint64_t>(LoadedVT.getSizeInBits());
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topperc wrote:

You're no longer getting the mask from the AND. Mask and ExpectedMask are always the same.

https://github.com/llvm/llvm-project/pull/136502