[llvm] [RISCV] Add disjoint or patterns for vwadd[u].vv (PR #136716)

[Luke Lau via llvm-commits]

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@@ -912,6 +912,25 @@ defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
 defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
 
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjoint_VV<SDNode extop, string instruction_name> {
+  foreach vtiToWti = AllWidenableIntVectors in {
+    defvar vti = vtiToWti.Vti;
+    defvar wti = vtiToWti.Wti;
+    let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+                                 GetVTypePredicates<wti>.Predicates) in {
+      def : Pat<(wti.Vector (extop (vti.Vector (or_disjoint vti.RegClass:$rs2, vti.RegClass:$rs1)))),
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lukel97 wrote:

Good point, I've added a .vx pattern too now.

Unless I'm missing something I don't think I can reuse the `VPatWidenBinarySDNode_VV_VX_WV_WX` multiclass because it's a different pattern. `VPatWidenOrDisjoint_VV` matches `ext (or a b)`,`VPatWidenBinarySDNode_VV_VX_WV_WX ` matches `or (ext a), (ext b)`

https://github.com/llvm/llvm-project/pull/136716