[llvm] [mlir] [AMDGPU][Verifier] Check address space of `alloca` instruction (PR #135820)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Doesn't it violate LLVM IR semantics since we treat a AS 0 type _as_ AS5? And also, what's the point of supporting AS 0 alloca?

No, especially since the address space interpretation is target specific. We can interpret alloca with a 0 address space as allocating in addrspace(5), that has an implicit addrspacecast to generic. This is what NVPTX does (except there it's a hard requirement, and there's a late lowering pass)

The point is to avoid the bug reports like the one you've presumably run into. This is a common one, people continuously just try to shove CPU IR through the backend and it fails on here. It is an IR producer bug, but we can also just deal with it. We can demote it from hard failure to suboptimal frontend IR that gives the backend more work to deal with 

https://github.com/llvm/llvm-project/pull/135820