[llvm] [Xtensa] Implement Xtensa S32C1I Option and atomics lowering. (PR #137134)

[Matt Arsenault via llvm-commits]

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@@ -114,9 +114,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
 }
 
 const MCPhysReg SRDecoderTable[] = {
-    Xtensa::SAR, 3,  Xtensa::ACCLO,      16, Xtensa::ACCHI,       17,
-    Xtensa::M0,  32, Xtensa::M1,         33, Xtensa::M2,          34,
-    Xtensa::M3,  35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73};
+    Xtensa::SAR, 3, Xtensa::ACCLO,      16, Xtensa::ACCHI,       17,
+    Xtensa::SCOMPARE1, 12, Xtensa::M0,  32, Xtensa::M1,          33,
+    Xtensa::M2,        34, Xtensa::M3,  35, Xtensa::WINDOWBASE,  72,
+    Xtensa::WINDOWSTART, 73, Xtensa::ATOMCTL, 99};
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arsenm wrote:

I don't understand this table, it's mixed MCPhysReg and then a random number? Should this be some kind of pair or struct? 

https://github.com/llvm/llvm-project/pull/137134