[llvm] [IA][RISCV] Add support for vp.load/vp.store with shufflevector (PR #135445)

[Min-Yih Hsu via llvm-commits]

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@@ -339,25 +371,48 @@ bool InterleavedAccessImpl::lowerInterleavedLoad(
     return false;
 
   bool BinOpShuffleChanged =
-      replaceBinOpShuffles(BinOpShuffles.getArrayRef(), Shuffles, LI);
-
-  LLVM_DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n");
+      replaceBinOpShuffles(BinOpShuffles.getArrayRef(), Shuffles, LoadOp);
+
+  // Check if the de-interleaved vp.load masks are the same.
+  unsigned ShuffleMaskLen = Shuffles[0]->getShuffleMask().size();
+  SmallVector<Constant *, 8> LaneMask(ShuffleMaskLen, nullptr);
+  if (auto *VPLoad = dyn_cast<VPIntrinsic>(LoadOp)) {
+    if (!isInterleavedConstantMask(
+            Factor, cast<ConstantVector>(VPLoad->getArgOperand(1)), LaneMask))
+      return false;
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mshockwave wrote:

I noticed that you remove the leaf value type from `getMask` in f218cd28d4b762846a84a24817396465b824710d. I have to added it back because in the case of load/vp.load + shufflevectors, the loaded vector can actually be wider than the aggregated type of individual lanes, for instance:
```
  %interleaved.vec = tail call <16 x i32> @llvm.vp.load.v16i32.p0(ptr %ptr, <16 x i1> (splat i1 true), i32 12)
  %v0 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
  %v1 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 1, i32 4, i32 7, i32 10>
  %v2 = shufflevector <16 x i32> %interleaved.vec, <16 x i32> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
```
in this case the factor is 3 and individual lane has a type of <4 x i32>, but the loaded type is <16 x i32> (wider than the aggregated <12 x i32>)

So to account for this, `getMask` needs the type of individual lane. This won't be a problem if we de-interleave by intrinsics, because in that case each lane always has a type of `LoadedType / Factor`.

https://github.com/llvm/llvm-project/pull/135445