[llvm] RISC-V: Support vectorizing FMINIMUMNUM and FMAXIMUMNUM (PR #135727)
YunQiang Su via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 21 18:17:32 PDT 2025
https://github.com/wzssyqa updated https://github.com/llvm/llvm-project/pull/135727
>From 893cfc279450e464f2e2c91c4df750cb17175adc Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Tue, 15 Apr 2025 09:53:04 +0800
Subject: [PATCH 1/5] RISC-V: Support vectorizing FMINIMUMNUM and FMAXIMUMNUM
RISC-V V extension support vfmax and vfmin, which follow IEEE754-2019.
We can use them directly.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 13 +-
.../LoopVectorize/RISCV/fminimumnum.ll | 736 +++++++++++++++++-
.../SLPVectorizer/RISCV/fminimumnum.ll | 313 +++-----
3 files changed, 854 insertions(+), 208 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 98fba9e86e88a..b9933339bf545 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -969,6 +969,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
static const unsigned ZvfhminZvfbfminPromoteOps[] = {
ISD::FMINNUM,
ISD::FMAXNUM,
+ ISD::FMINIMUMNUM,
+ ISD::FMAXIMUMNUM,
ISD::FADD,
ISD::FSUB,
ISD::FMUL,
@@ -1037,7 +1039,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// Expand various condition codes (explained above).
setCondCodeAction(VFPCCToExpand, VT, Expand);
- setOperationAction({ISD::FMINNUM, ISD::FMAXNUM}, VT, Legal);
+ setOperationAction(
+ {ISD::FMINNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM}, VT,
+ Legal);
setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, VT, Custom);
setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND,
@@ -1455,7 +1459,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FDIV,
ISD::FNEG, ISD::FABS, ISD::FCOPYSIGN, ISD::FSQRT,
ISD::FMA, ISD::FMINNUM, ISD::FMAXNUM,
- ISD::IS_FPCLASS, ISD::FMAXIMUM, ISD::FMINIMUM},
+ ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM, ISD::IS_FPCLASS,
+ ISD::FMAXIMUM, ISD::FMINIMUM},
VT, Custom);
setOperationAction({ISD::FTRUNC, ISD::FCEIL, ISD::FFLOOR, ISD::FROUND,
@@ -6913,9 +6918,11 @@ static unsigned getRISCVVLOp(SDValue Op) {
case ISD::VP_FP_TO_UINT:
return RISCVISD::VFCVT_RTZ_XU_F_VL;
case ISD::FMINNUM:
+ case ISD::FMINIMUMNUM:
case ISD::VP_FMINNUM:
return RISCVISD::VFMIN_VL;
case ISD::FMAXNUM:
+ case ISD::FMAXIMUMNUM:
case ISD::VP_FMAXNUM:
return RISCVISD::VFMAX_VL;
case ISD::LRINT:
@@ -7951,6 +7958,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::FMA:
case ISD::FMINNUM:
case ISD::FMAXNUM:
+ case ISD::FMINIMUMNUM:
+ case ISD::FMAXIMUMNUM:
if (isPromotedOpNeedingSplit(Op, Subtarget))
return SplitVectorOp(Op, DAG);
[[fallthrough]];
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll b/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
index b97fa2499cfd5..1319454b7a1a1 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/fminimumnum.ll
@@ -1,14 +1,62 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; FIXME: fmaximumnum/fminimumnum have no vectorizing support yet.
-; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+zvfh,+v,+zfh" -S < %s | FileCheck %s
+; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+v,+zvfh" -S < %s | FileCheck %s
+; RUN: opt --passes=loop-vectorize --mtriple=riscv64 -mattr="+v,+zvfhmin" -S < %s | FileCheck %s --check-prefix=ZVFHMIN
define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
; CHECK-LABEL: define void @fmin32(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP8]], 4
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP15]], 4
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP4]], 4
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP16]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP7]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP9]], 4
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP18]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP19]], 4
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x float>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 4 x float> @llvm.minimumnum.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]], <vscale x 4 x float> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i32 0
+; CHECK-NEXT: store <vscale x 4 x float> [[TMP17]], ptr [[TMP11]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -18,10 +66,76 @@ define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store float [[OUT]], ptr [[ARRAYIDX4]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin32(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0:[0-9]+]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 4
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 4
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP14]], align 4
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x float>, ptr [[TMP16]], align 4
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 4 x float> @llvm.minimumnum.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]], <vscale x 4 x float> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw float, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 4 x float> [[TMP17]], ptr [[TMP19]], align 4
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call float @llvm.minimumnum.f32(float [[IN1]], float [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store float [[OUT]], ptr [[ARRAYIDX4]], align 4
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -48,9 +162,56 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-LABEL: define void @fmax32(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP8]], 4
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP15]], 4
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP4]], 4
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP16]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP7]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP9]], 4
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP18]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP19]], 4
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP3]], align 4
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw float, ptr [[TMP5]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x float>, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 4 x float> @llvm.maximumnum.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]], <vscale x 4 x float> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw float, ptr [[TMP10]], i32 0
+; CHECK-NEXT: store <vscale x 4 x float> [[TMP17]], ptr [[TMP11]], align 4
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -60,10 +221,76 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store float [[OUT]], ptr [[ARRAYIDX4]], align 4
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax32(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 4
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 4
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 4
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 4
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 4
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw float, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, ptr [[TMP14]], align 4
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw float, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x float>, ptr [[TMP16]], align 4
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 4 x float> @llvm.maximumnum.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD]], <vscale x 4 x float> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw float, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 4 x float> [[TMP17]], ptr [[TMP19]], align 4
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load float, ptr [[ARRAYIDX]], align 4
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call float @llvm.maximumnum.f32(float [[IN1]], float [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x float], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store float [[OUT]], ptr [[ARRAYIDX4]], align 4
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -90,9 +317,56 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-LABEL: define void @fmin64(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP8]], 2
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP15]], 2
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP4]], 8
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP16]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP7]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP9]], 2
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP18]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP19]], 2
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw double, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw double, ptr [[TMP5]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x double>, ptr [[TMP6]], align 8
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 2 x double> @llvm.minimumnum.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD]], <vscale x 2 x double> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw double, ptr [[TMP10]], i32 0
+; CHECK-NEXT: store <vscale x 2 x double> [[TMP17]], ptr [[TMP11]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load double, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -102,10 +376,76 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store double [[OUT]], ptr [[ARRAYIDX4]], align 8
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin64(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 8
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 8
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 2
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 2
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw double, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP14]], align 8
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw double, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x double>, ptr [[TMP16]], align 8
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 2 x double> @llvm.minimumnum.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD]], <vscale x 2 x double> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw double, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 2 x double> [[TMP17]], ptr [[TMP19]], align 8
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load double, ptr [[ARRAYIDX]], align 8
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call double @llvm.minimumnum.f64(double [[IN1]], double [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store double [[OUT]], ptr [[ARRAYIDX4]], align 8
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -132,9 +472,56 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-LABEL: define void @fmax64(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP8]], 2
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP4:%.*]] = mul i64 [[TMP15]], 2
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP4]], 8
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP16]]
+; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 8
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP7]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP9]], 2
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP18]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP19]], 2
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw double, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP3]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds nuw double, ptr [[TMP5]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x double>, ptr [[TMP6]], align 8
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 2 x double> @llvm.maximumnum.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD]], <vscale x 2 x double> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds nuw double, ptr [[TMP10]], i32 0
+; CHECK-NEXT: store <vscale x 2 x double> [[TMP17]], ptr [[TMP11]], align 8
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load double, ptr [[ARRAYIDX]], align 8
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -144,10 +531,76 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store double [[OUT]], ptr [[ARRAYIDX4]], align 8
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax64(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 2
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 8
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 8
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 2
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 2
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw double, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x double>, ptr [[TMP14]], align 8
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw double, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 2 x double>, ptr [[TMP16]], align 8
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 2 x double> @llvm.maximumnum.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD]], <vscale x 2 x double> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw double, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 2 x double> [[TMP17]], ptr [[TMP19]], align 8
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load double, ptr [[ARRAYIDX]], align 8
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load double, ptr [[ARRAYIDX2]], align 8
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call double @llvm.maximumnum.f64(double [[IN1]], double [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x double], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store double [[OUT]], ptr [[ARRAYIDX4]], align 8
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -174,9 +627,56 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-LABEL: define void @fmin16(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP6]], 8
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 8
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP18]]
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP16]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP19]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw half, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP3]], align 2
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw half, ptr [[TMP4]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 2
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x half> @llvm.minimumnum.nxv8f16(<vscale x 8 x half> [[WIDE_LOAD]], <vscale x 8 x half> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw half, ptr [[TMP7]], i32 0
+; CHECK-NEXT: store <vscale x 8 x half> [[TMP17]], ptr [[TMP8]], align 2
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load half, ptr [[ARRAYIDX]], align 2
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -186,10 +686,76 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store half [[OUT]], ptr [[ARRAYIDX4]], align 2
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin16(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 8
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 2
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw half, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP14]], align 2
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw half, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 8 x half>, ptr [[TMP16]], align 2
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 8 x half> @llvm.minimumnum.nxv8f16(<vscale x 8 x half> [[WIDE_LOAD]], <vscale x 8 x half> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw half, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 8 x half> [[TMP17]], ptr [[TMP19]], align 2
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load half, ptr [[ARRAYIDX]], align 2
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load half, ptr [[ARRAYIDX2]], align 2
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call half @llvm.minimumnum.f16(half [[IN1]], half [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store half [[OUT]], ptr [[ARRAYIDX4]], align 2
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -216,9 +782,56 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-LABEL: define void @fmax16(
; CHECK-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; CHECK-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; CHECK-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP13:%.*]] = mul i64 [[TMP6]], 8
+; CHECK-NEXT: [[TMP14:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP13]])
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP14]]
+; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; CHECK: [[VECTOR_MEMCHECK]]:
+; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 8
+; CHECK-NEXT: [[TMP18:%.*]] = mul i64 [[TMP16]], 2
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP18]]
+; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP16]], 2
+; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; CHECK-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP1]], [[TMP19]]
+; CHECK-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; CHECK-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK: [[VECTOR_PH]]:
+; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds nuw half, ptr [[TMP2]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP3]], align 2
+; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds nuw half, ptr [[TMP4]], i32 0
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 8 x half>, ptr [[TMP5]], align 2
+; CHECK-NEXT: [[TMP17:%.*]] = call <vscale x 8 x half> @llvm.maximumnum.nxv8f16(<vscale x 8 x half> [[WIDE_LOAD]], <vscale x 8 x half> [[WIDE_LOAD5]])
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds nuw half, ptr [[TMP7]], i32 0
+; CHECK-NEXT: store <vscale x 8 x half> [[TMP17]], ptr [[TMP8]], align 2
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK: [[MIDDLE_BLOCK]]:
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
; CHECK: [[FOR_BODY]]:
-; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT: [[IN1:%.*]] = load half, ptr [[ARRAYIDX]], align 2
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDVARS_IV]]
@@ -228,10 +841,76 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; CHECK-NEXT: store half [[OUT]], ptr [[ARRAYIDX4]], align 2
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 4096
-; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]]
+; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax16(
+; ZVFHMIN-SAME: ptr noundef readonly captures(none) [[INPUT1:%.*]], ptr noundef readonly captures(none) [[INPUT2:%.*]], ptr noundef writeonly captures(none) [[OUTPUT:%.*]]) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*]]:
+; ZVFHMIN-NEXT: [[INPUT23:%.*]] = ptrtoint ptr [[INPUT2]] to i64
+; ZVFHMIN-NEXT: [[INPUT12:%.*]] = ptrtoint ptr [[INPUT1]] to i64
+; ZVFHMIN-NEXT: [[OUTPUT1:%.*]] = ptrtoint ptr [[OUTPUT]] to i64
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 8
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call i64 @llvm.umax.i64(i64 16, i64 [[TMP1]])
+; ZVFHMIN-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 4096, [[TMP2]]
+; ZVFHMIN-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
+; ZVFHMIN: [[VECTOR_MEMCHECK]]:
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2
+; ZVFHMIN-NEXT: [[TMP6:%.*]] = sub i64 [[OUTPUT1]], [[INPUT12]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
+; ZVFHMIN-NEXT: [[TMP7:%.*]] = mul i64 [[TMP4]], 2
+; ZVFHMIN-NEXT: [[TMP8:%.*]] = sub i64 [[OUTPUT1]], [[INPUT23]]
+; ZVFHMIN-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP8]], [[TMP7]]
+; ZVFHMIN-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
+; ZVFHMIN-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; ZVFHMIN: [[VECTOR_PH]]:
+; ZVFHMIN-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8
+; ZVFHMIN-NEXT: [[N_MOD_VF:%.*]] = urem i64 4096, [[TMP10]]
+; ZVFHMIN-NEXT: [[N_VEC:%.*]] = sub i64 4096, [[N_MOD_VF]]
+; ZVFHMIN-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
+; ZVFHMIN-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8
+; ZVFHMIN-NEXT: br label %[[VECTOR_BODY:.*]]
+; ZVFHMIN: [[VECTOR_BODY]]:
+; ZVFHMIN-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; ZVFHMIN-NEXT: [[TMP13:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP14:%.*]] = getelementptr inbounds nuw half, ptr [[TMP13]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 8 x half>, ptr [[TMP14]], align 2
+; ZVFHMIN-NEXT: [[TMP15:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP16:%.*]] = getelementptr inbounds nuw half, ptr [[TMP15]], i32 0
+; ZVFHMIN-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 8 x half>, ptr [[TMP16]], align 2
+; ZVFHMIN-NEXT: [[TMP17:%.*]] = call <vscale x 8 x half> @llvm.maximumnum.nxv8f16(<vscale x 8 x half> [[WIDE_LOAD]], <vscale x 8 x half> [[WIDE_LOAD5]])
+; ZVFHMIN-NEXT: [[TMP18:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[INDEX]]
+; ZVFHMIN-NEXT: [[TMP19:%.*]] = getelementptr inbounds nuw half, ptr [[TMP18]], i32 0
+; ZVFHMIN-NEXT: store <vscale x 8 x half> [[TMP17]], ptr [[TMP19]], align 2
+; ZVFHMIN-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]]
+; ZVFHMIN-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; ZVFHMIN: [[MIDDLE_BLOCK]]:
+; ZVFHMIN-NEXT: [[CMP_N:%.*]] = icmp eq i64 4096, [[N_VEC]]
+; ZVFHMIN-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
+; ZVFHMIN: [[SCALAR_PH]]:
+; ZVFHMIN-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
+; ZVFHMIN-NEXT: br label %[[FOR_BODY:.*]]
+; ZVFHMIN: [[FOR_BODY]]:
+; ZVFHMIN-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[FOR_BODY]] ]
+; ZVFHMIN-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT1]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN1:%.*]] = load half, ptr [[ARRAYIDX]], align 2
+; ZVFHMIN-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[INPUT2]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: [[IN2:%.*]] = load half, ptr [[ARRAYIDX2]], align 2
+; ZVFHMIN-NEXT: [[OUT:%.*]] = tail call half @llvm.maximumnum.f16(half [[IN1]], half [[IN2]])
+; ZVFHMIN-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds nuw [4096 x half], ptr [[OUTPUT]], i64 0, i64 [[IV]]
+; ZVFHMIN-NEXT: store half [[OUT]], ptr [[ARRAYIDX4]], align 2
+; ZVFHMIN-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; ZVFHMIN-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_NEXT]], 4096
+; ZVFHMIN-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
+; ZVFHMIN: [[EXIT]]:
+; ZVFHMIN-NEXT: ret void
+;
entry:
br label %for.body
@@ -253,3 +932,34 @@ exit:
}
declare half @llvm.maximumnum.f16(half, half)
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}
+; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}
+; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
+; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}
+; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}
+; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]}
+;.
+; ZVFHMIN: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; ZVFHMIN: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; ZVFHMIN: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; ZVFHMIN: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
+; ZVFHMIN: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; ZVFHMIN: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
+; ZVFHMIN: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
+; ZVFHMIN: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}
+; ZVFHMIN: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
+; ZVFHMIN: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}
+; ZVFHMIN: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
+; ZVFHMIN: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}
+; ZVFHMIN: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}
+; ZVFHMIN: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]}
+;.
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/fminimumnum.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/fminimumnum.ll
index 920abfad776e0..4d43f3f3e55f0 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/fminimumnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/fminimumnum.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
-; RUN: opt --passes=slp-vectorizer --mtriple=riscv64 -mattr="+zvfh,+v,+zfh" -S < %s | FileCheck %s
+; RUN: opt --passes=slp-vectorizer --mtriple=riscv64 -mattr="+v,+zvfh" -S < %s | FileCheck %s
+; RUN: opt --passes=slp-vectorizer --mtriple=riscv64 -mattr="+v,+zvfhmin" -S < %s | FileCheck %s --check-prefix=ZVFHMIN
@input1_f32 = global [9 x float] zeroinitializer, align 16
@input2_f32 = global [9 x float] zeroinitializer, align 16
@@ -15,44 +16,29 @@ define void @fmin32() {
; CHECK-LABEL: define void @fmin32(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @input1_f32, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @input2_f32, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP0]], float [[TMP1]])
-; CHECK-NEXT: store float [[TMP2]], ptr @output_f32, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP5:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP3]], float [[TMP4]])
-; CHECK-NEXT: store float [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP8:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP6]], float [[TMP7]])
-; CHECK-NEXT: store float [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP11:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP9]], float [[TMP10]])
-; CHECK-NEXT: store float [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP12:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP13:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP14:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP12]], float [[TMP13]])
-; CHECK-NEXT: store float [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP16:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP17:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP15]], float [[TMP16]])
-; CHECK-NEXT: store float [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP18:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP20:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP18]], float [[TMP19]])
-; CHECK-NEXT: store float [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP21:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 28), align 4
-; CHECK-NEXT: [[TMP22:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 28), align 4
-; CHECK-NEXT: [[TMP23:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP21]], float [[TMP22]])
-; CHECK-NEXT: store float [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 28), align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr @input1_f32, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @input2_f32, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.minimumnum.v8f32(<8 x float> [[TMP0]], <8 x float> [[TMP1]])
+; CHECK-NEXT: store <8 x float> [[TMP2]], ptr @output_f32, align 16
; CHECK-NEXT: [[TMP24:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 32), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 32), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call float @llvm.minimumnum.f32(float [[TMP24]], float [[TMP25]])
; CHECK-NEXT: store float [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 32), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin32(
+; ZVFHMIN-SAME: ) #[[ATTR0:[0-9]+]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr @input1_f32, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @input2_f32, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.minimumnum.v8f32(<8 x float> [[TMP0]], <8 x float> [[TMP1]])
+; ZVFHMIN-NEXT: store <8 x float> [[TMP2]], ptr @output_f32, align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 32), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 32), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call float @llvm.minimumnum.f32(float [[INPUT8_1]], float [[INPUT8_2]])
+; ZVFHMIN-NEXT: store float [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 32), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load float, ptr @input1_f32, align 16
%input0_1 = load float, ptr @input2_f32, align 16
@@ -99,44 +85,29 @@ define void @fmax32() {
; CHECK-LABEL: define void @fmax32(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load float, ptr @input1_f32, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @input2_f32, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP0]], float [[TMP1]])
-; CHECK-NEXT: store float [[TMP2]], ptr @output_f32, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP5:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP3]], float [[TMP4]])
-; CHECK-NEXT: store float [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 4), align 4
-; CHECK-NEXT: [[TMP6:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP8:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP6]], float [[TMP7]])
-; CHECK-NEXT: store float [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 8), align 8
-; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP11:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP9]], float [[TMP10]])
-; CHECK-NEXT: store float [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 12), align 4
-; CHECK-NEXT: [[TMP12:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP13:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP14:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP12]], float [[TMP13]])
-; CHECK-NEXT: store float [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 16), align 16
-; CHECK-NEXT: [[TMP15:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP16:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP17:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP15]], float [[TMP16]])
-; CHECK-NEXT: store float [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 20), align 4
-; CHECK-NEXT: [[TMP18:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP20:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP18]], float [[TMP19]])
-; CHECK-NEXT: store float [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 24), align 8
-; CHECK-NEXT: [[TMP21:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 28), align 4
-; CHECK-NEXT: [[TMP22:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 28), align 4
-; CHECK-NEXT: [[TMP23:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP21]], float [[TMP22]])
-; CHECK-NEXT: store float [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 28), align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr @input1_f32, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @input2_f32, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.maximumnum.v8f32(<8 x float> [[TMP0]], <8 x float> [[TMP1]])
+; CHECK-NEXT: store <8 x float> [[TMP2]], ptr @output_f32, align 16
; CHECK-NEXT: [[TMP24:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 32), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 32), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call float @llvm.maximumnum.f32(float [[TMP24]], float [[TMP25]])
; CHECK-NEXT: store float [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 32), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax32(
+; ZVFHMIN-SAME: ) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <8 x float>, ptr @input1_f32, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @input2_f32, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.maximumnum.v8f32(<8 x float> [[TMP0]], <8 x float> [[TMP1]])
+; ZVFHMIN-NEXT: store <8 x float> [[TMP2]], ptr @output_f32, align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input1_f32, i64 32), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load float, ptr getelementptr inbounds nuw (i8, ptr @input2_f32, i64 32), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call float @llvm.maximumnum.f32(float [[INPUT8_1]], float [[INPUT8_2]])
+; ZVFHMIN-NEXT: store float [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f32, i64 32), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load float, ptr @input1_f32, align 16
%input0_1 = load float, ptr @input2_f32, align 16
@@ -183,44 +154,37 @@ define void @fmin64() {
; CHECK-LABEL: define void @fmin64(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr @input1_f64, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr @input2_f64, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP0]], double [[TMP1]])
-; CHECK-NEXT: store double [[TMP2]], ptr @output_f64, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP5:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP3]], double [[TMP4]])
-; CHECK-NEXT: store double [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP8:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP6]], double [[TMP7]])
-; CHECK-NEXT: store double [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP10:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP11:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP9]], double [[TMP10]])
-; CHECK-NEXT: store double [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP12:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP13:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP14:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP12]], double [[TMP13]])
-; CHECK-NEXT: store double [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP15:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP16:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP17:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP15]], double [[TMP16]])
-; CHECK-NEXT: store double [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP18:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP19:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP20:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP18]], double [[TMP19]])
-; CHECK-NEXT: store double [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP21:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 56), align 8
-; CHECK-NEXT: [[TMP22:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 56), align 8
-; CHECK-NEXT: [[TMP23:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP21]], double [[TMP22]])
-; CHECK-NEXT: store double [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 56), align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr @input1_f64, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @input2_f64, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> [[TMP0]], <4 x double> [[TMP1]])
+; CHECK-NEXT: store <4 x double> [[TMP2]], ptr @output_f64, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
+; CHECK-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
+; CHECK-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> [[TMP3]], <4 x double> [[TMP4]])
+; CHECK-NEXT: store <4 x double> [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
; CHECK-NEXT: [[TMP24:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 64), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 64), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call double @llvm.minimumnum.f64(double [[TMP24]], double [[TMP25]])
; CHECK-NEXT: store double [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 64), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin64(
+; ZVFHMIN-SAME: ) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr @input1_f64, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @input2_f64, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> [[TMP0]], <4 x double> [[TMP1]])
+; ZVFHMIN-NEXT: store <4 x double> [[TMP2]], ptr @output_f64, align 16
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> [[TMP3]], <4 x double> [[TMP4]])
+; ZVFHMIN-NEXT: store <4 x double> [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 64), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 64), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call double @llvm.minimumnum.f64(double [[INPUT8_1]], double [[INPUT8_2]])
+; ZVFHMIN-NEXT: store double [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 64), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load double, ptr @input1_f64, align 16
%input0_1 = load double, ptr @input2_f64, align 16
@@ -267,44 +231,37 @@ define void @fmax64() {
; CHECK-LABEL: define void @fmax64(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr @input1_f64, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load double, ptr @input2_f64, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP0]], double [[TMP1]])
-; CHECK-NEXT: store double [[TMP2]], ptr @output_f64, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP4:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP5:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP3]], double [[TMP4]])
-; CHECK-NEXT: store double [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 8), align 8
-; CHECK-NEXT: [[TMP6:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP7:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP8:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP6]], double [[TMP7]])
-; CHECK-NEXT: store double [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 16), align 16
-; CHECK-NEXT: [[TMP9:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP10:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP11:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP9]], double [[TMP10]])
-; CHECK-NEXT: store double [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 24), align 8
-; CHECK-NEXT: [[TMP12:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP13:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP14:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP12]], double [[TMP13]])
-; CHECK-NEXT: store double [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
-; CHECK-NEXT: [[TMP15:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP16:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP17:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP15]], double [[TMP16]])
-; CHECK-NEXT: store double [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 40), align 8
-; CHECK-NEXT: [[TMP18:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP19:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP20:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP18]], double [[TMP19]])
-; CHECK-NEXT: store double [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 48), align 16
-; CHECK-NEXT: [[TMP21:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 56), align 8
-; CHECK-NEXT: [[TMP22:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 56), align 8
-; CHECK-NEXT: [[TMP23:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP21]], double [[TMP22]])
-; CHECK-NEXT: store double [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 56), align 8
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr @input1_f64, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @input2_f64, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> [[TMP0]], <4 x double> [[TMP1]])
+; CHECK-NEXT: store <4 x double> [[TMP2]], ptr @output_f64, align 16
+; CHECK-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
+; CHECK-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
+; CHECK-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> [[TMP3]], <4 x double> [[TMP4]])
+; CHECK-NEXT: store <4 x double> [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
; CHECK-NEXT: [[TMP24:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 64), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 64), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call double @llvm.maximumnum.f64(double [[TMP24]], double [[TMP25]])
; CHECK-NEXT: store double [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 64), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax64(
+; ZVFHMIN-SAME: ) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <4 x double>, ptr @input1_f64, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @input2_f64, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> [[TMP0]], <4 x double> [[TMP1]])
+; ZVFHMIN-NEXT: store <4 x double> [[TMP2]], ptr @output_f64, align 16
+; ZVFHMIN-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[TMP5:%.*]] = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> [[TMP3]], <4 x double> [[TMP4]])
+; ZVFHMIN-NEXT: store <4 x double> [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 32), align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input1_f64, i64 64), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load double, ptr getelementptr inbounds nuw (i8, ptr @input2_f64, i64 64), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call double @llvm.maximumnum.f64(double [[INPUT8_1]], double [[INPUT8_2]])
+; ZVFHMIN-NEXT: store double [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f64, i64 64), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load double, ptr @input1_f64, align 16
%input0_1 = load double, ptr @input2_f64, align 16
@@ -351,44 +308,29 @@ define void @fmin16() {
; CHECK-LABEL: define void @fmin16(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @input1_f16, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load half, ptr @input2_f16, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP0]], half [[TMP1]])
-; CHECK-NEXT: store half [[TMP2]], ptr @output_f16, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP4:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP5:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP3]], half [[TMP4]])
-; CHECK-NEXT: store half [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP6:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP8:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP6]], half [[TMP7]])
-; CHECK-NEXT: store half [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP10:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP11:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP9]], half [[TMP10]])
-; CHECK-NEXT: store half [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP12:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP13:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP14:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP12]], half [[TMP13]])
-; CHECK-NEXT: store half [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP15:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP16:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP17:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP15]], half [[TMP16]])
-; CHECK-NEXT: store half [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP18:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP19:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP20:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP18]], half [[TMP19]])
-; CHECK-NEXT: store half [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP21:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 14), align 2
-; CHECK-NEXT: [[TMP22:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 14), align 2
-; CHECK-NEXT: [[TMP23:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP21]], half [[TMP22]])
-; CHECK-NEXT: store half [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 14), align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr @input1_f16, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr @input2_f16, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.minimumnum.v8f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]])
+; CHECK-NEXT: store <8 x half> [[TMP2]], ptr @output_f16, align 16
; CHECK-NEXT: [[TMP24:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 16), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 16), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call half @llvm.minimumnum.f16(half [[TMP24]], half [[TMP25]])
; CHECK-NEXT: store half [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 16), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmin16(
+; ZVFHMIN-SAME: ) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr @input1_f16, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr @input2_f16, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.minimumnum.v8f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]])
+; ZVFHMIN-NEXT: store <8 x half> [[TMP2]], ptr @output_f16, align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 16), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 16), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call half @llvm.minimumnum.f16(half [[INPUT8_1]], half [[INPUT8_2]])
+; ZVFHMIN-NEXT: store half [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 16), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load half, ptr @input1_f16, align 16
%input0_1 = load half, ptr @input2_f16, align 16
@@ -435,44 +377,29 @@ define void @fmax16() {
; CHECK-LABEL: define void @fmax16(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load half, ptr @input1_f16, align 16
-; CHECK-NEXT: [[TMP1:%.*]] = load half, ptr @input2_f16, align 16
-; CHECK-NEXT: [[TMP2:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP0]], half [[TMP1]])
-; CHECK-NEXT: store half [[TMP2]], ptr @output_f16, align 16
-; CHECK-NEXT: [[TMP3:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP4:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP5:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP3]], half [[TMP4]])
-; CHECK-NEXT: store half [[TMP5]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 2), align 2
-; CHECK-NEXT: [[TMP6:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP8:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP6]], half [[TMP7]])
-; CHECK-NEXT: store half [[TMP8]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 4), align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP10:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP11:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP9]], half [[TMP10]])
-; CHECK-NEXT: store half [[TMP11]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 6), align 2
-; CHECK-NEXT: [[TMP12:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP13:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP14:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP12]], half [[TMP13]])
-; CHECK-NEXT: store half [[TMP14]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 8), align 8
-; CHECK-NEXT: [[TMP15:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP16:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP17:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP15]], half [[TMP16]])
-; CHECK-NEXT: store half [[TMP17]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 10), align 2
-; CHECK-NEXT: [[TMP18:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP19:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP20:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP18]], half [[TMP19]])
-; CHECK-NEXT: store half [[TMP20]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 12), align 4
-; CHECK-NEXT: [[TMP21:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 14), align 2
-; CHECK-NEXT: [[TMP22:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 14), align 2
-; CHECK-NEXT: [[TMP23:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP21]], half [[TMP22]])
-; CHECK-NEXT: store half [[TMP23]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 14), align 2
+; CHECK-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr @input1_f16, align 16
+; CHECK-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr @input2_f16, align 16
+; CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.maximumnum.v8f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]])
+; CHECK-NEXT: store <8 x half> [[TMP2]], ptr @output_f16, align 16
; CHECK-NEXT: [[TMP24:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 16), align 16
; CHECK-NEXT: [[TMP25:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 16), align 16
; CHECK-NEXT: [[TMP26:%.*]] = tail call half @llvm.maximumnum.f16(half [[TMP24]], half [[TMP25]])
; CHECK-NEXT: store half [[TMP26]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 16), align 16
; CHECK-NEXT: ret void
;
+; ZVFHMIN-LABEL: define void @fmax16(
+; ZVFHMIN-SAME: ) #[[ATTR0]] {
+; ZVFHMIN-NEXT: [[ENTRY:.*:]]
+; ZVFHMIN-NEXT: [[TMP0:%.*]] = load <8 x half>, ptr @input1_f16, align 16
+; ZVFHMIN-NEXT: [[TMP1:%.*]] = load <8 x half>, ptr @input2_f16, align 16
+; ZVFHMIN-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.maximumnum.v8f16(<8 x half> [[TMP0]], <8 x half> [[TMP1]])
+; ZVFHMIN-NEXT: store <8 x half> [[TMP2]], ptr @output_f16, align 16
+; ZVFHMIN-NEXT: [[INPUT8_1:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input1_f16, i64 16), align 16
+; ZVFHMIN-NEXT: [[INPUT8_2:%.*]] = load half, ptr getelementptr inbounds nuw (i8, ptr @input2_f16, i64 16), align 16
+; ZVFHMIN-NEXT: [[OUTPUT8:%.*]] = tail call half @llvm.maximumnum.f16(half [[INPUT8_1]], half [[INPUT8_2]])
+; ZVFHMIN-NEXT: store half [[OUTPUT8]], ptr getelementptr inbounds nuw (i8, ptr @output_f16, i64 16), align 16
+; ZVFHMIN-NEXT: ret void
+;
entry:
%input0_0 = load half, ptr @input1_f16, align 16
%input0_1 = load half, ptr @input2_f16, align 16
>From 4b30f20e08ee86b5cac42b6a04476a2347c3ceeb Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Wed, 16 Apr 2025 11:07:05 +0800
Subject: [PATCH 2/5] Fix vscale support
Add CodeGen testcase
---
.../Target/RISCV/RISCVInstrInfoVSDPatterns.td | 2 +
.../RISCV/vector-maximumnum-minimumnum.ll | 1090 +++++++++++++++++
2 files changed, 1092 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index b2c5261ae6c2d..de306a341336b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1337,6 +1337,8 @@ foreach vti = AllFloatVectors in {
// 13.11. Vector Floating-Point MIN/MAX Instructions
defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN", isSEWAware=1>;
defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX", isSEWAware=1>;
+defm : VPatBinaryFPSDNode_VV_VF<fminimumnum, "PseudoVFMIN", isSEWAware=1>;
+defm : VPatBinaryFPSDNode_VV_VF<fmaximumnum, "PseudoVFMAX", isSEWAware=1>;
// 13.13. Vector Floating-Point Compare Instructions
defm : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
diff --git a/llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll b/llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll
new file mode 100644
index 0000000000000..6ca7ee2e5364a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll
@@ -0,0 +1,1090 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=riscv64-linux-gnu --mattr=+v,+zvfh < %s | FileCheck %s --check-prefix=ZVFH
+; RUN: llc --mtriple=riscv64-linux-gnu --mattr=+v,+zvfhmin,+zfh < %s | FileCheck %s --check-prefix=ZVFHMIN
+
+;;;;;;;;;;;;;;;; max_f64
+define double @max_f64(double %a, double %b) {
+; ZVFH-LABEL: max_f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fmax.d fa0, fa0, fa1
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmax.d fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call double @llvm.maximumnum.f64(double %a, double %b)
+ ret double %c
+}
+
+define <2 x double> @max_v2f64(<2 x double> %a, <2 x double> %b) {
+; ZVFH-LABEL: max_v2f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v2f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x double> @llvm.maximumnum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %c
+}
+
+define <3 x double> @max_v3f64(<3 x double> %a, <3 x double> %b) {
+; ZVFH-LABEL: max_v3f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v3f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <3 x double> @llvm.maximumnum.v3f64(<3 x double> %a, <3 x double> %b)
+ ret <3 x double> %c
+}
+
+define <4 x double> @max_v4f64(<4 x double> %a, <4 x double> %b) {
+; ZVFH-LABEL: max_v4f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v4f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x double> @llvm.maximumnum.v4f64(<4 x double> %a, <4 x double> %b)
+ ret <4 x double> %c
+}
+
+;;;;;;;;;;;;;;;;;; max_f32
+define float @max_f32(float %a, float %b) {
+; ZVFH-LABEL: max_f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fmax.s fa0, fa0, fa1
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmax.s fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call float @llvm.maximumnum.f32(float %a, float %b)
+ ret float %c
+}
+
+define <2 x float> @max_v2f32(<2 x float> %a, <2 x float> %b) {
+; ZVFH-LABEL: max_v2f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v2f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x float> @llvm.maximumnum.v2f32(<2 x float> %a, <2 x float> %b)
+ ret <2 x float> %c
+}
+
+define <3 x float> @max_v3f32(<3 x float> %a, <3 x float> %b) {
+; ZVFH-LABEL: max_v3f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v3f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <3 x float> @llvm.maximumnum.v3f32(<3 x float> %a, <3 x float> %b)
+ ret <3 x float> %c
+}
+
+define <4 x float> @max_v4f32(<4 x float> %a, <4 x float> %b) {
+; ZVFH-LABEL: max_v4f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v4f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x float> @llvm.maximumnum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %c
+}
+
+define <5 x float> @max_v5f32(<5 x float> %a, <5 x float> %b) {
+; ZVFH-LABEL: max_v5f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v5f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <5 x float> @llvm.maximumnum.v5f32(<5 x float> %a, <5 x float> %b)
+ ret <5 x float> %c
+}
+
+define <8 x float> @max_v8f32(<8 x float> %a, <8 x float> %b) {
+; ZVFH-LABEL: max_v8f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v8f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <8 x float> @llvm.maximumnum.v8f32(<8 x float> %a, <8 x float> %b)
+ ret <8 x float> %c
+}
+
+;;;;;;;;;;;;;;;;;; max_f16
+define half @max_f16(half %a, half %b) {
+; ZVFH-LABEL: max_f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fcvt.s.h fa5, fa1
+; ZVFH-NEXT: fcvt.s.h fa4, fa0
+; ZVFH-NEXT: fmax.s fa5, fa4, fa5
+; ZVFH-NEXT: fcvt.h.s fa0, fa5
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmax.h fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call half @llvm.maximumnum.f16(half %a, half %b)
+ ret half %c
+}
+
+define <2 x half> @max_v2f16(<2 x half> %a, <2 x half> %b) {
+; ZVFH-LABEL: max_v2f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v2f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x half> @llvm.maximumnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %c
+}
+
+define <4 x half> @max_v4f16(<4 x half> %a, <4 x half> %b) {
+; ZVFH-LABEL: max_v4f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v4f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v9, v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x half> @llvm.maximumnum.v4f16(<4 x half> %a, <4 x half> %b)
+ ret <4 x half> %c
+}
+
+define <8 x half> @max_v8f16(<8 x half> %a, <8 x half> %b) {
+; ZVFH-LABEL: max_v8f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v8f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v10, v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <8 x half> @llvm.maximumnum.v8f16(<8 x half> %a, <8 x half> %b)
+ ret <8 x half> %c
+}
+
+define <9 x half> @max_v9f16(<9 x half> %a, <9 x half> %b) {
+; ZVFH-LABEL: max_v9f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v9f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <9 x half> @llvm.maximumnum.v9f16(<9 x half> %a, <9 x half> %b)
+ ret <9 x half> %c
+}
+
+define <16 x half> @max_v16f16(<16 x half> %a, <16 x half> %b) {
+; ZVFH-LABEL: max_v16f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: max_v16f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v12, v16, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <16 x half> @llvm.maximumnum.v16f16(<16 x half> %a, <16 x half> %b)
+ ret <16 x half> %c
+}
+
+;;;;;;;;;;;;;;;; min_f64
+define double @min_f64(double %a, double %b) {
+; ZVFH-LABEL: min_f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fmin.d fa0, fa0, fa1
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmin.d fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call double @llvm.minimumnum.f64(double %a, double %b)
+ ret double %c
+}
+
+define <2 x double> @min_v2f64(<2 x double> %a, <2 x double> %b) {
+; ZVFH-LABEL: min_v2f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v2f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x double> @llvm.minimumnum.v2f64(<2 x double> %a, <2 x double> %b)
+ ret <2 x double> %c
+}
+
+define <3 x double> @min_v3f64(<3 x double> %a, <3 x double> %b) {
+; ZVFH-LABEL: min_v3f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v3f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <3 x double> @llvm.minimumnum.v3f64(<3 x double> %a, <3 x double> %b)
+ ret <3 x double> %c
+}
+
+define <4 x double> @min_v4f64(<4 x double> %a, <4 x double> %b) {
+; ZVFH-LABEL: min_v4f64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v4f64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x double> @llvm.minimumnum.v4f64(<4 x double> %a, <4 x double> %b)
+ ret <4 x double> %c
+}
+
+;;;;;;;;;;;;;;;;;; min_f32
+define float @min_f32(float %a, float %b) {
+; ZVFH-LABEL: min_f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fmin.s fa0, fa0, fa1
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmin.s fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call float @llvm.minimumnum.f32(float %a, float %b)
+ ret float %c
+}
+
+define <2 x float> @min_v2f32(<2 x float> %a, <2 x float> %b) {
+; ZVFH-LABEL: min_v2f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v2f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x float> @llvm.minimumnum.v2f32(<2 x float> %a, <2 x float> %b)
+ ret <2 x float> %c
+}
+
+define <3 x float> @min_v3f32(<3 x float> %a, <3 x float> %b) {
+; ZVFH-LABEL: min_v3f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v3f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <3 x float> @llvm.minimumnum.v3f32(<3 x float> %a, <3 x float> %b)
+ ret <3 x float> %c
+}
+
+define <4 x float> @min_v4f32(<4 x float> %a, <4 x float> %b) {
+; ZVFH-LABEL: min_v4f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v4f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x float> @llvm.minimumnum.v4f32(<4 x float> %a, <4 x float> %b)
+ ret <4 x float> %c
+}
+
+define <5 x float> @min_v5f32(<5 x float> %a, <5 x float> %b) {
+; ZVFH-LABEL: min_v5f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v5f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <5 x float> @llvm.minimumnum.v5f32(<5 x float> %a, <5 x float> %b)
+ ret <5 x float> %c
+}
+
+define <8 x float> @min_v8f32(<8 x float> %a, <8 x float> %b) {
+; ZVFH-LABEL: min_v8f32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v8f32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <8 x float> @llvm.minimumnum.v8f32(<8 x float> %a, <8 x float> %b)
+ ret <8 x float> %c
+}
+
+;;;;;;;;;;;;;;;;;; min_f16
+define half @min_f16(half %a, half %b) {
+; ZVFH-LABEL: min_f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: fcvt.s.h fa5, fa1
+; ZVFH-NEXT: fcvt.s.h fa4, fa0
+; ZVFH-NEXT: fmin.s fa5, fa4, fa5
+; ZVFH-NEXT: fcvt.h.s fa0, fa5
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: fmin.h fa0, fa0, fa1
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call half @llvm.minimumnum.f16(half %a, half %b)
+ ret half %c
+}
+
+define <2 x half> @min_v2f16(<2 x half> %a, <2 x half> %b) {
+; ZVFH-LABEL: min_v2f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v2f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <2 x half> @llvm.minimumnum.v2f16(<2 x half> %a, <2 x half> %b)
+ ret <2 x half> %c
+}
+
+define <4 x half> @min_v4f16(<4 x half> %a, <4 x half> %b) {
+; ZVFH-LABEL: min_v4f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v4f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v9, v9, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <4 x half> @llvm.minimumnum.v4f16(<4 x half> %a, <4 x half> %b)
+ ret <4 x half> %c
+}
+
+define <8 x half> @min_v8f16(<8 x half> %a, <8 x half> %b) {
+; ZVFH-LABEL: min_v8f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v9
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v8f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v9
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v10, v12, v10
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v10
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <8 x half> @llvm.minimumnum.v8f16(<8 x half> %a, <8 x half> %b)
+ ret <8 x half> %c
+}
+
+define <9 x half> @min_v9f16(<9 x half> %a, <9 x half> %b) {
+; ZVFH-LABEL: min_v9f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v9f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <9 x half> @llvm.minimumnum.v9f16(<9 x half> %a, <9 x half> %b)
+ ret <9 x half> %c
+}
+
+define <16 x half> @min_v16f16(<16 x half> %a, <16 x half> %b) {
+; ZVFH-LABEL: min_v16f16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: min_v16f16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v10
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v12, v16, v12
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v12
+; ZVFHMIN-NEXT: ret
+entry:
+ %c = call <16 x half> @llvm.minimumnum.v16f16(<16 x half> %a, <16 x half> %b)
+ ret <16 x half> %c
+}
+
+;; vscale
+define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmin32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a5, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: srli a3, a5, 1
+; ZVFH-NEXT: neg a6, a3
+; ZVFH-NEXT: and a4, a6, a4
+; ZVFH-NEXT: slli a5, a5, 1
+; ZVFH-NEXT: vsetvli a6, zero, e32, m2, ta, ma
+; ZVFH-NEXT: .LBB32_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re32.v v8, (a0)
+; ZVFH-NEXT: vl2re32.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB32_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmin32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: srli a3, a5, 1
+; ZVFHMIN-NEXT: neg a6, a3
+; ZVFHMIN-NEXT: and a4, a6, a4
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB32_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re32.v v8, (a0)
+; ZVFHMIN-NEXT: vl2re32.v v10, (a1)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: vs2r.v v8, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB32_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 4
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 4
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x float], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw float, ptr %13, i32 0
+ %wide.load = load <vscale x 4 x float>, ptr %14, align 4
+ %15 = getelementptr inbounds nuw [4096 x float], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw float, ptr %15, i32 0
+ %wide.load5 = load <vscale x 4 x float>, ptr %16, align 4
+ %17 = call <vscale x 4 x float> @llvm.minimumnum.nxv4f32(<vscale x 4 x float> %wide.load, <vscale x 4 x float> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x float], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw float, ptr %18, i32 0
+ store <vscale x 4 x float> %17, ptr %19, align 4
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
+
+define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmax32:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a5, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: srli a3, a5, 1
+; ZVFH-NEXT: neg a6, a3
+; ZVFH-NEXT: and a4, a6, a4
+; ZVFH-NEXT: slli a5, a5, 1
+; ZVFH-NEXT: vsetvli a6, zero, e32, m2, ta, ma
+; ZVFH-NEXT: .LBB33_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re32.v v8, (a0)
+; ZVFH-NEXT: vl2re32.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB33_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmax32:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: srli a3, a5, 1
+; ZVFHMIN-NEXT: neg a6, a3
+; ZVFHMIN-NEXT: and a4, a6, a4
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e32, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB33_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re32.v v8, (a0)
+; ZVFHMIN-NEXT: vl2re32.v v10, (a1)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: vs2r.v v8, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB33_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 4
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 4
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x float], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw float, ptr %13, i32 0
+ %wide.load = load <vscale x 4 x float>, ptr %14, align 4
+ %15 = getelementptr inbounds nuw [4096 x float], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw float, ptr %15, i32 0
+ %wide.load5 = load <vscale x 4 x float>, ptr %16, align 4
+ %17 = call <vscale x 4 x float> @llvm.maximumnum.nxv4f32(<vscale x 4 x float> %wide.load, <vscale x 4 x float> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x float], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw float, ptr %18, i32 0
+ store <vscale x 4 x float> %17, ptr %19, align 4
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
+
+define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmin64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a5, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: srli a3, a5, 2
+; ZVFH-NEXT: neg a6, a3
+; ZVFH-NEXT: and a4, a6, a4
+; ZVFH-NEXT: slli a5, a5, 1
+; ZVFH-NEXT: vsetvli a6, zero, e64, m2, ta, ma
+; ZVFH-NEXT: .LBB34_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re64.v v8, (a0)
+; ZVFH-NEXT: vl2re64.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB34_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmin64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: srli a3, a5, 2
+; ZVFHMIN-NEXT: neg a6, a3
+; ZVFHMIN-NEXT: and a4, a6, a4
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e64, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB34_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re64.v v8, (a0)
+; ZVFHMIN-NEXT: vl2re64.v v10, (a1)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfmin.vv v8, v8, v10
+; ZVFHMIN-NEXT: vs2r.v v8, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB34_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 2
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 2
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x double], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw double, ptr %13, i32 0
+ %wide.load = load <vscale x 2 x double>, ptr %14, align 8
+ %15 = getelementptr inbounds nuw [4096 x double], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw double, ptr %15, i32 0
+ %wide.load5 = load <vscale x 2 x double>, ptr %16, align 8
+ %17 = call <vscale x 2 x double> @llvm.minimumnum.nxv2f64(<vscale x 2 x double> %wide.load, <vscale x 2 x double> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x double], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw double, ptr %18, i32 0
+ store <vscale x 2 x double> %17, ptr %19, align 8
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
+
+define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmax64:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a5, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: srli a3, a5, 2
+; ZVFH-NEXT: neg a6, a3
+; ZVFH-NEXT: and a4, a6, a4
+; ZVFH-NEXT: slli a5, a5, 1
+; ZVFH-NEXT: vsetvli a6, zero, e64, m2, ta, ma
+; ZVFH-NEXT: .LBB35_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re64.v v8, (a0)
+; ZVFH-NEXT: vl2re64.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB35_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmax64:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a5, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: srli a3, a5, 2
+; ZVFHMIN-NEXT: neg a6, a3
+; ZVFHMIN-NEXT: and a4, a6, a4
+; ZVFHMIN-NEXT: slli a5, a5, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e64, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB35_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re64.v v8, (a0)
+; ZVFHMIN-NEXT: vl2re64.v v10, (a1)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfmax.vv v8, v8, v10
+; ZVFHMIN-NEXT: vs2r.v v8, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB35_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 2
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 2
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x double], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw double, ptr %13, i32 0
+ %wide.load = load <vscale x 2 x double>, ptr %14, align 8
+ %15 = getelementptr inbounds nuw [4096 x double], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw double, ptr %15, i32 0
+ %wide.load5 = load <vscale x 2 x double>, ptr %16, align 8
+ %17 = call <vscale x 2 x double> @llvm.maximumnum.nxv2f64(<vscale x 2 x double> %wide.load, <vscale x 2 x double> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x double], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw double, ptr %18, i32 0
+ store <vscale x 2 x double> %17, ptr %19, align 8
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
+
+define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmin16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: neg a5, a3
+; ZVFH-NEXT: and a4, a5, a4
+; ZVFH-NEXT: slli a5, a3, 1
+; ZVFH-NEXT: vsetvli a6, zero, e16, m2, ta, ma
+; ZVFH-NEXT: .LBB36_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re16.v v8, (a0)
+; ZVFH-NEXT: vl2re16.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmin.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB36_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmin16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: neg a5, a3
+; ZVFHMIN-NEXT: and a4, a5, a4
+; ZVFHMIN-NEXT: slli a5, a3, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB36_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re16.v v12, (a1)
+; ZVFHMIN-NEXT: vl2re16.v v16, (a0)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmin.vv v8, v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
+; ZVFHMIN-NEXT: vs2r.v v12, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB36_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 8
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 8
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x half], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw half, ptr %13, i32 0
+ %wide.load = load <vscale x 8 x half>, ptr %14, align 2
+ %15 = getelementptr inbounds nuw [4096 x half], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw half, ptr %15, i32 0
+ %wide.load5 = load <vscale x 8 x half>, ptr %16, align 2
+ %17 = call <vscale x 8 x half> @llvm.minimumnum.nxv8f16(<vscale x 8 x half> %wide.load, <vscale x 8 x half> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x half], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw half, ptr %18, i32 0
+ store <vscale x 8 x half> %17, ptr %19, align 2
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
+
+define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef readonly captures(none) %input2, ptr noundef writeonly captures(none) %output) {
+; ZVFH-LABEL: fmax16:
+; ZVFH: # %bb.0: # %entry
+; ZVFH-NEXT: csrr a3, vlenb
+; ZVFH-NEXT: lui a4, 1
+; ZVFH-NEXT: neg a5, a3
+; ZVFH-NEXT: and a4, a5, a4
+; ZVFH-NEXT: slli a5, a3, 1
+; ZVFH-NEXT: vsetvli a6, zero, e16, m2, ta, ma
+; ZVFH-NEXT: .LBB37_1: # %vector.body
+; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFH-NEXT: vl2re16.v v8, (a0)
+; ZVFH-NEXT: vl2re16.v v10, (a1)
+; ZVFH-NEXT: sub a4, a4, a3
+; ZVFH-NEXT: add a1, a1, a5
+; ZVFH-NEXT: vfmax.vv v8, v8, v10
+; ZVFH-NEXT: vs2r.v v8, (a2)
+; ZVFH-NEXT: add a2, a2, a5
+; ZVFH-NEXT: add a0, a0, a5
+; ZVFH-NEXT: bnez a4, .LBB37_1
+; ZVFH-NEXT: # %bb.2: # %exit
+; ZVFH-NEXT: ret
+;
+; ZVFHMIN-LABEL: fmax16:
+; ZVFHMIN: # %bb.0: # %entry
+; ZVFHMIN-NEXT: csrr a3, vlenb
+; ZVFHMIN-NEXT: lui a4, 1
+; ZVFHMIN-NEXT: neg a5, a3
+; ZVFHMIN-NEXT: and a4, a5, a4
+; ZVFHMIN-NEXT: slli a5, a3, 1
+; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: .LBB37_1: # %vector.body
+; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
+; ZVFHMIN-NEXT: vl2re16.v v12, (a1)
+; ZVFHMIN-NEXT: vl2re16.v v16, (a0)
+; ZVFHMIN-NEXT: sub a4, a4, a3
+; ZVFHMIN-NEXT: add a1, a1, a5
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v12
+; ZVFHMIN-NEXT: vfwcvt.f.f.v v12, v16
+; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; ZVFHMIN-NEXT: vfmax.vv v8, v12, v8
+; ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
+; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v8
+; ZVFHMIN-NEXT: vs2r.v v12, (a2)
+; ZVFHMIN-NEXT: add a2, a2, a5
+; ZVFHMIN-NEXT: add a0, a0, a5
+; ZVFHMIN-NEXT: bnez a4, .LBB37_1
+; ZVFHMIN-NEXT: # %bb.2: # %exit
+; ZVFHMIN-NEXT: ret
+entry:
+ %input23 = ptrtoint ptr %input2 to i64
+ %input12 = ptrtoint ptr %input1 to i64
+ %output1 = ptrtoint ptr %output to i64
+ br label %vector.ph
+
+vector.ph:
+ %9 = call i64 @llvm.vscale.i64()
+ %10 = mul i64 %9, 8
+ %n.mod.vf = urem i64 4096, %10
+ %n.vec = sub i64 4096, %n.mod.vf
+ %11 = call i64 @llvm.vscale.i64()
+ %12 = mul i64 %11, 8
+ br label %vector.body
+
+vector.body: ; preds = %vector.body, %vector.ph
+ %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
+ %13 = getelementptr inbounds nuw [4096 x half], ptr %input1, i64 0, i64 %index
+ %14 = getelementptr inbounds nuw half, ptr %13, i32 0
+ %wide.load = load <vscale x 8 x half>, ptr %14, align 2
+ %15 = getelementptr inbounds nuw [4096 x half], ptr %input2, i64 0, i64 %index
+ %16 = getelementptr inbounds nuw half, ptr %15, i32 0
+ %wide.load5 = load <vscale x 8 x half>, ptr %16, align 2
+ %17 = call <vscale x 8 x half> @llvm.maximumnum.nxv8f16(<vscale x 8 x half> %wide.load, <vscale x 8 x half> %wide.load5)
+ %18 = getelementptr inbounds nuw [4096 x half], ptr %output, i64 0, i64 %index
+ %19 = getelementptr inbounds nuw half, ptr %18, i32 0
+ store <vscale x 8 x half> %17, ptr %19, align 2
+ %index.next = add nuw i64 %index, %12
+ %20 = icmp eq i64 %index.next, %n.vec
+ br i1 %20, label %exit, label %vector.body
+
+exit: ; preds = %middle.block, %for.body
+ ret void
+}
>From a589c9787f7bef310804c94288136c4a472ad928 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Mon, 21 Apr 2025 08:29:05 +0800
Subject: [PATCH 3/5] move into rvv subidr
---
.../maximumnum-minimumnum.ll} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename llvm/test/CodeGen/RISCV/{vector-maximumnum-minimumnum.ll => rvv/maximumnum-minimumnum.ll} (100%)
diff --git a/llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll b/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
similarity index 100%
rename from llvm/test/CodeGen/RISCV/vector-maximumnum-minimumnum.ll
rename to llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
>From cb9336c08ee58bbcef4adfdc8d1a5110b51014d2 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Mon, 21 Apr 2025 08:34:22 +0800
Subject: [PATCH 4/5] remove scale tests
---
.../RISCV/rvv/maximumnum-minimumnum.ll | 102 ------------------
1 file changed, 102 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll b/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
index 6ca7ee2e5364a..33d40faa9d400 100644
--- a/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
@@ -2,22 +2,6 @@
; RUN: llc --mtriple=riscv64-linux-gnu --mattr=+v,+zvfh < %s | FileCheck %s --check-prefix=ZVFH
; RUN: llc --mtriple=riscv64-linux-gnu --mattr=+v,+zvfhmin,+zfh < %s | FileCheck %s --check-prefix=ZVFHMIN
-;;;;;;;;;;;;;;;; max_f64
-define double @max_f64(double %a, double %b) {
-; ZVFH-LABEL: max_f64:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fmax.d fa0, fa0, fa1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: max_f64:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmax.d fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call double @llvm.maximumnum.f64(double %a, double %b)
- ret double %c
-}
-
define <2 x double> @max_v2f64(<2 x double> %a, <2 x double> %b) {
; ZVFH-LABEL: max_v2f64:
; ZVFH: # %bb.0: # %entry
@@ -69,22 +53,6 @@ entry:
ret <4 x double> %c
}
-;;;;;;;;;;;;;;;;;; max_f32
-define float @max_f32(float %a, float %b) {
-; ZVFH-LABEL: max_f32:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fmax.s fa0, fa0, fa1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: max_f32:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmax.s fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call float @llvm.maximumnum.f32(float %a, float %b)
- ret float %c
-}
-
define <2 x float> @max_v2f32(<2 x float> %a, <2 x float> %b) {
; ZVFH-LABEL: max_v2f32:
; ZVFH: # %bb.0: # %entry
@@ -170,25 +138,6 @@ entry:
ret <8 x float> %c
}
-;;;;;;;;;;;;;;;;;; max_f16
-define half @max_f16(half %a, half %b) {
-; ZVFH-LABEL: max_f16:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fcvt.s.h fa5, fa1
-; ZVFH-NEXT: fcvt.s.h fa4, fa0
-; ZVFH-NEXT: fmax.s fa5, fa4, fa5
-; ZVFH-NEXT: fcvt.h.s fa0, fa5
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: max_f16:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmax.h fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call half @llvm.maximumnum.f16(half %a, half %b)
- ret half %c
-}
-
define <2 x half> @max_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVFH-LABEL: max_v2f16:
; ZVFH: # %bb.0: # %entry
@@ -299,22 +248,6 @@ entry:
ret <16 x half> %c
}
-;;;;;;;;;;;;;;;; min_f64
-define double @min_f64(double %a, double %b) {
-; ZVFH-LABEL: min_f64:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fmin.d fa0, fa0, fa1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: min_f64:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmin.d fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call double @llvm.minimumnum.f64(double %a, double %b)
- ret double %c
-}
-
define <2 x double> @min_v2f64(<2 x double> %a, <2 x double> %b) {
; ZVFH-LABEL: min_v2f64:
; ZVFH: # %bb.0: # %entry
@@ -366,22 +299,6 @@ entry:
ret <4 x double> %c
}
-;;;;;;;;;;;;;;;;;; min_f32
-define float @min_f32(float %a, float %b) {
-; ZVFH-LABEL: min_f32:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fmin.s fa0, fa0, fa1
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: min_f32:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmin.s fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call float @llvm.minimumnum.f32(float %a, float %b)
- ret float %c
-}
-
define <2 x float> @min_v2f32(<2 x float> %a, <2 x float> %b) {
; ZVFH-LABEL: min_v2f32:
; ZVFH: # %bb.0: # %entry
@@ -467,25 +384,6 @@ entry:
ret <8 x float> %c
}
-;;;;;;;;;;;;;;;;;; min_f16
-define half @min_f16(half %a, half %b) {
-; ZVFH-LABEL: min_f16:
-; ZVFH: # %bb.0: # %entry
-; ZVFH-NEXT: fcvt.s.h fa5, fa1
-; ZVFH-NEXT: fcvt.s.h fa4, fa0
-; ZVFH-NEXT: fmin.s fa5, fa4, fa5
-; ZVFH-NEXT: fcvt.h.s fa0, fa5
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: min_f16:
-; ZVFHMIN: # %bb.0: # %entry
-; ZVFHMIN-NEXT: fmin.h fa0, fa0, fa1
-; ZVFHMIN-NEXT: ret
-entry:
- %c = call half @llvm.minimumnum.f16(half %a, half %b)
- ret half %c
-}
-
define <2 x half> @min_v2f16(<2 x half> %a, <2 x half> %b) {
; ZVFH-LABEL: min_v2f16:
; ZVFH: # %bb.0: # %entry
>From 16784711c19dba4acef05b3f464806b3acba90f7 Mon Sep 17 00:00:00 2001
From: YunQiang Su <yunqiang at isrc.iscas.ac.cn>
Date: Tue, 22 Apr 2025 09:17:10 +0800
Subject: [PATCH 5/5] update testcase
---
.../RISCV/rvv/maximumnum-minimumnum.ll | 48 +++++++++----------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll b/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
index 33d40faa9d400..9e903b0fa7a76 100644
--- a/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/maximumnum-minimumnum.ll
@@ -505,7 +505,7 @@ define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a6, a4
; ZVFH-NEXT: slli a5, a5, 1
; ZVFH-NEXT: vsetvli a6, zero, e32, m2, ta, ma
-; ZVFH-NEXT: .LBB32_1: # %vector.body
+; ZVFH-NEXT: .LBB26_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re32.v v8, (a0)
; ZVFH-NEXT: vl2re32.v v10, (a1)
@@ -515,7 +515,7 @@ define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB32_1
+; ZVFH-NEXT: bnez a4, .LBB26_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -528,7 +528,7 @@ define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a6, a4
; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB32_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB26_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re32.v v8, (a0)
; ZVFHMIN-NEXT: vl2re32.v v10, (a1)
@@ -538,7 +538,7 @@ define void @fmin32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v8, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB32_1
+; ZVFHMIN-NEXT: bnez a4, .LBB26_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
@@ -586,7 +586,7 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a6, a4
; ZVFH-NEXT: slli a5, a5, 1
; ZVFH-NEXT: vsetvli a6, zero, e32, m2, ta, ma
-; ZVFH-NEXT: .LBB33_1: # %vector.body
+; ZVFH-NEXT: .LBB27_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re32.v v8, (a0)
; ZVFH-NEXT: vl2re32.v v10, (a1)
@@ -596,7 +596,7 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB33_1
+; ZVFH-NEXT: bnez a4, .LBB27_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -609,7 +609,7 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a6, a4
; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e32, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB33_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB27_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re32.v v8, (a0)
; ZVFHMIN-NEXT: vl2re32.v v10, (a1)
@@ -619,7 +619,7 @@ define void @fmax32(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v8, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB33_1
+; ZVFHMIN-NEXT: bnez a4, .LBB27_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
@@ -667,7 +667,7 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a6, a4
; ZVFH-NEXT: slli a5, a5, 1
; ZVFH-NEXT: vsetvli a6, zero, e64, m2, ta, ma
-; ZVFH-NEXT: .LBB34_1: # %vector.body
+; ZVFH-NEXT: .LBB28_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re64.v v8, (a0)
; ZVFH-NEXT: vl2re64.v v10, (a1)
@@ -677,7 +677,7 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB34_1
+; ZVFH-NEXT: bnez a4, .LBB28_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -690,7 +690,7 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a6, a4
; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e64, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB34_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB28_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re64.v v8, (a0)
; ZVFHMIN-NEXT: vl2re64.v v10, (a1)
@@ -700,7 +700,7 @@ define void @fmin64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v8, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB34_1
+; ZVFHMIN-NEXT: bnez a4, .LBB28_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
@@ -748,7 +748,7 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a6, a4
; ZVFH-NEXT: slli a5, a5, 1
; ZVFH-NEXT: vsetvli a6, zero, e64, m2, ta, ma
-; ZVFH-NEXT: .LBB35_1: # %vector.body
+; ZVFH-NEXT: .LBB29_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re64.v v8, (a0)
; ZVFH-NEXT: vl2re64.v v10, (a1)
@@ -758,7 +758,7 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB35_1
+; ZVFH-NEXT: bnez a4, .LBB29_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -771,7 +771,7 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a6, a4
; ZVFHMIN-NEXT: slli a5, a5, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e64, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB35_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB29_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re64.v v8, (a0)
; ZVFHMIN-NEXT: vl2re64.v v10, (a1)
@@ -781,7 +781,7 @@ define void @fmax64(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v8, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB35_1
+; ZVFHMIN-NEXT: bnez a4, .LBB29_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
@@ -828,7 +828,7 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a5, a4
; ZVFH-NEXT: slli a5, a3, 1
; ZVFH-NEXT: vsetvli a6, zero, e16, m2, ta, ma
-; ZVFH-NEXT: .LBB36_1: # %vector.body
+; ZVFH-NEXT: .LBB30_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re16.v v8, (a0)
; ZVFH-NEXT: vl2re16.v v10, (a1)
@@ -838,7 +838,7 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB36_1
+; ZVFH-NEXT: bnez a4, .LBB30_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -850,7 +850,7 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a5, a4
; ZVFHMIN-NEXT: slli a5, a3, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB36_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB30_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re16.v v12, (a1)
; ZVFHMIN-NEXT: vl2re16.v v16, (a0)
@@ -865,7 +865,7 @@ define void @fmin16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v12, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB36_1
+; ZVFHMIN-NEXT: bnez a4, .LBB30_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
@@ -912,7 +912,7 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: and a4, a5, a4
; ZVFH-NEXT: slli a5, a3, 1
; ZVFH-NEXT: vsetvli a6, zero, e16, m2, ta, ma
-; ZVFH-NEXT: .LBB37_1: # %vector.body
+; ZVFH-NEXT: .LBB31_1: # %vector.body
; ZVFH-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFH-NEXT: vl2re16.v v8, (a0)
; ZVFH-NEXT: vl2re16.v v10, (a1)
@@ -922,7 +922,7 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFH-NEXT: vs2r.v v8, (a2)
; ZVFH-NEXT: add a2, a2, a5
; ZVFH-NEXT: add a0, a0, a5
-; ZVFH-NEXT: bnez a4, .LBB37_1
+; ZVFH-NEXT: bnez a4, .LBB31_1
; ZVFH-NEXT: # %bb.2: # %exit
; ZVFH-NEXT: ret
;
@@ -934,7 +934,7 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: and a4, a5, a4
; ZVFHMIN-NEXT: slli a5, a3, 1
; ZVFHMIN-NEXT: vsetvli a6, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: .LBB37_1: # %vector.body
+; ZVFHMIN-NEXT: .LBB31_1: # %vector.body
; ZVFHMIN-NEXT: # =>This Inner Loop Header: Depth=1
; ZVFHMIN-NEXT: vl2re16.v v12, (a1)
; ZVFHMIN-NEXT: vl2re16.v v16, (a0)
@@ -949,7 +949,7 @@ define void @fmax16(ptr noundef readonly captures(none) %input1, ptr noundef rea
; ZVFHMIN-NEXT: vs2r.v v12, (a2)
; ZVFHMIN-NEXT: add a2, a2, a5
; ZVFHMIN-NEXT: add a0, a0, a5
-; ZVFHMIN-NEXT: bnez a4, .LBB37_1
+; ZVFHMIN-NEXT: bnez a4, .LBB31_1
; ZVFHMIN-NEXT: # %bb.2: # %exit
; ZVFHMIN-NEXT: ret
entry:
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