[llvm] a2f00e1 - [RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)
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Thu Apr 24 01:36:20 PDT 2025
Author: Luke Lau
Date: 2025-04-24T16:36:15+08:00
New Revision: a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
URL: https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3
DIFF: https://github.com/llvm/llvm-project/commit/a2f00e1f8f124667339b94ffa144c0ff0d6ae3b3.diff
LOG: [RISCV] Add fixed-length patterns for disjoint or patterns for vwadd[u].v{v,x} (#136824)
This is the fixed-length equivalent of #136716.
The pattern we need to match is ({s,z}ext_vl (or_vl disjoint a, b)).
This only allows or_vls with an undef passthru, which allows us to
ignore its mask and vl and just take it from the {s,z}ext_vl.
A riscv_or_vl_is_add_oneuse PatFrag is added to mirror or_is_add in
RISCVInstrInfo.td.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index f80cbc9e2fb5e..fe36def4fda2f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -497,6 +497,16 @@ let HasOneUse = 1 in {
node:$E),
(riscv_add_vl node:$A, node:$B, node:$C,
node:$D, node:$E)>;
+ def riscv_or_vl_is_add_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
+ node:$E),
+ (riscv_or_vl node:$A, node:$B, node:$C,
+ node:$D, node:$E), [{
+ if (N->getFlags().hasDisjoint())
+ return true;
+ KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
+ KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
+ return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+ }]>;
def riscv_sub_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D,
node:$E),
(riscv_sub_vl node:$A, node:$B, node:$C,
@@ -2016,6 +2026,41 @@ foreach vtiToWti = AllWidenableIntVectors in {
}
}
+// DAGCombiner::hoistLogicOpWithSameOpcodeHands may hoist disjoint ors
+// to (ext (or disjoint (a, b)))
+multiclass VPatWidenOrDisjointVL_VV_VX<SDNode extop, string instruction_name> {
+ foreach vtiToWti = AllWidenableIntVectors in {
+ defvar vti = vtiToWti.Vti;
+ defvar wti = vtiToWti.Wti;
+ let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
+ GetVTypePredicates<wti>.Predicates) in {
+ def : Pat<(wti.Vector
+ (extop
+ (vti.Vector
+ (riscv_or_vl_is_add_oneuse
+ vti.RegClass:$rs2, vti.RegClass:$rs1,
+ undef, srcvalue, srcvalue)),
+ VMV0:$vm, VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK")
+ (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+ vti.RegClass:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
+ def : Pat<(wti.Vector
+ (extop
+ (vti.Vector
+ (riscv_or_vl_is_add_oneuse
+ vti.RegClass:$rs2, (SplatPat (XLenVT GPR:$rs1)),
+ undef, srcvalue, srcvalue)),
+ VMV0:$vm, VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK")
+ (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
+ GPR:$rs1, VMV0:$vm, GPR:$vl, vti.Log2SEW, TA_MA)>;
+ }
+ }
+}
+
+defm : VPatWidenOrDisjointVL_VV_VX<riscv_sext_vl, "PseudoVWADD">;
+defm : VPatWidenOrDisjointVL_VV_VX<riscv_zext_vl, "PseudoVWADDU">;
+
// 11.3. Vector Integer Extension
defm : VPatExtendVL_V<riscv_zext_vl, "PseudoVZEXT", "VF2",
AllFractionableVF2IntVectors>;
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index 4346e90a1f5f7..b39fff64b1090 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -899,9 +899,8 @@ define <4 x i32> @vwaddu_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
; CHECK-LABEL: vwaddu_vv_disjoint_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vor.vv v9, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v8, v9
+; CHECK-NEXT: vwaddu.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
%y.i32 = zext <4 x i16> %y.i16 to <4 x i32>
@@ -913,9 +912,8 @@ define <4 x i32> @vwadd_vv_disjoint_or(<4 x i16> %x.i16, <4 x i16> %y.i16) {
; CHECK-LABEL: vwadd_vv_disjoint_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vor.vv v9, v8, v9
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v8, v9
+; CHECK-NEXT: vwadd.vv v10, v8, v9
+; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
%y.i32 = sext <4 x i16> %y.i16 to <4 x i32>
@@ -927,9 +925,8 @@ define <4 x i32> @vwaddu_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
; CHECK-LABEL: vwaddu_vx_disjoint_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vor.vx v9, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vzext.vf2 v8, v9
+; CHECK-NEXT: vwaddu.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%x.i32 = zext <4 x i16> %x.i16 to <4 x i32>
%y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
@@ -943,9 +940,8 @@ define <4 x i32> @vwadd_vx_disjoint_or(<4 x i16> %x.i16, i16 %y.i16) {
; CHECK-LABEL: vwadd_vx_disjoint_or:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vor.vx v9, v8, a0
-; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-NEXT: vsext.vf2 v8, v9
+; CHECK-NEXT: vwadd.vx v9, v8, a0
+; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%x.i32 = sext <4 x i16> %x.i16 to <4 x i32>
%y.head = insertelement <4 x i16> poison, i16 %y.i16, i32 0
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