[llvm] [LV] Fix missing entry in willGenerateVectors (PR #136712)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 22 11:53:55 PDT 2025
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/136712
>From dafa614df51f693f6289d2f88d9cf2d87f3c696f Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 22 Apr 2025 16:26:02 +0100
Subject: [PATCH 1/4] [LV] Fix missing entry in willGenerateVectors
willGenerateVectors switches on opcodes of a recipe, but Histogram is
missing in the switch statement, which could cause a crash in some
cases. The crash was initially observed when developing another patch:
no test case is included with this patch, as the bug is evident.
---
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 32c3435ccb38d..4f607f4732aba 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -4460,6 +4460,7 @@ static bool willGenerateVectors(VPlan &Plan, ElementCount VF,
case VPDef::VPWidenSelectSC:
case VPDef::VPBlendSC:
case VPDef::VPFirstOrderRecurrencePHISC:
+ case VPDef::VPHistogramSC:
case VPDef::VPWidenPHISC:
case VPDef::VPWidenIntOrFpInductionSC:
case VPDef::VPWidenPointerInductionSC:
>From 221e5112c57e786ecf4efa9bd3a7303c6bef8977 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 22 Apr 2025 17:08:28 +0100
Subject: [PATCH 2/4] [LV] Add test for crash
---
.../LoopVectorize/AArch64/sve2-histcnt.ll | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
index 56cea996f3d80..0a2a41ccada3a 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
@@ -753,6 +753,29 @@ for.exit:
ret void
}
+; The histogram operation generates vectors. This example used to crash
+; due to a missing entry in a switch statement.
+define void @histogram_generates_vectors_crash(ptr %data_array) {
+entry:
+ br label %for.body
+
+for.body:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
+ %gep.indices = getelementptr [1048576 x i32], ptr null, i64 %iv
+ %l.idx = load i32, ptr %gep.indices, align 4
+ %idxprom5 = sext i32 %l.idx to i64
+ %gep.bucket = getelementptr [1048576 x i32], ptr %data_array, i64 %idxprom5
+ %l.bucket = load i32, ptr %gep.bucket, align 4
+ %inc = add i32 %l.bucket, 0
+ store i32 %inc, ptr %gep.bucket, align 4
+ %iv.next = add i64 %iv, 1
+ %exitcond = icmp eq i64 %iv, 1
+ br i1 %exitcond, label %for.exit, label %for.body
+
+for.exit:
+ ret void
+}
+
attributes #0 = { "target-features"="+sve2" vscale_range(1,16) }
!0 = distinct !{!0, !1}
>From ec61aa4e0c5c3531c068dff3e83318db4e5b718c Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 22 Apr 2025 18:23:13 +0100
Subject: [PATCH 3/4] [LV] Generate CHECK lines for crash for completeness
---
.../Transforms/LoopVectorize/AArch64/sve2-histcnt.ll | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
index 0a2a41ccada3a..e431ba04d66c7 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
@@ -756,6 +756,16 @@ for.exit:
; The histogram operation generates vectors. This example used to crash
; due to a missing entry in a switch statement.
define void @histogram_generates_vectors_crash(ptr %data_array) {
+; CHECK-LABEL: define void @histogram_generates_vectors_crash(
+; CHECK-SAME: ptr [[DATA_ARRAY:%.*]]) {
+; CHECK-NEXT: entry:
+; CHECK-NEXT: br label [[FOR_BODY:%.*]]
+; CHECK: for.body:
+; CHECK-NEXT: store i1 true, ptr poison, align 1
+; CHECK-NEXT: br i1 poison, label [[FOR_EXIT:%.*]], label [[FOR_BODY]]
+; CHECK: for.exit:
+; CHECK-NEXT: ret void
+;
entry:
br label %for.body
>From 508464793e9ee5d4cf5ba8af36d33e1c61972b20 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <ramkumar.ramachandra at codasip.com>
Date: Tue, 22 Apr 2025 19:52:05 +0100
Subject: [PATCH 4/4] [LV] Strip immediate UB
---
.../Transforms/LoopVectorize/AArch64/sve2-histcnt.ll | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
index e431ba04d66c7..9bf3c00baa4e1 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve2-histcnt.ll
@@ -755,14 +755,16 @@ for.exit:
; The histogram operation generates vectors. This example used to crash
; due to a missing entry in a switch statement.
-define void @histogram_generates_vectors_crash(ptr %data_array) {
+define void @histogram_generates_vectors_crash(ptr %data_array, ptr noalias %indices) {
; CHECK-LABEL: define void @histogram_generates_vectors_crash(
-; CHECK-SAME: ptr [[DATA_ARRAY:%.*]]) {
+; CHECK-SAME: ptr [[DATA_ARRAY:%.*]], ptr noalias [[INDICES:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
-; CHECK-NEXT: store i1 true, ptr poison, align 1
-; CHECK-NEXT: br i1 poison, label [[FOR_EXIT:%.*]], label [[FOR_BODY]]
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[EXITCOND]], label [[FOR_EXIT:%.*]], label [[FOR_BODY]]
; CHECK: for.exit:
; CHECK-NEXT: ret void
;
@@ -771,7 +773,7 @@ entry:
for.body:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ]
- %gep.indices = getelementptr [1048576 x i32], ptr null, i64 %iv
+ %gep.indices = getelementptr [1048576 x i32], ptr %indices, i64 %iv
%l.idx = load i32, ptr %gep.indices, align 4
%idxprom5 = sext i32 %l.idx to i64
%gep.bucket = getelementptr [1048576 x i32], ptr %data_array, i64 %idxprom5
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