[llvm] [AMDGPU][True16][CodeGen] update wwm reg sorting check condition (PR #135053)

[Brox Chen via llvm-commits]

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@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            wwm_skip_shift_16bit_reg
+tracksRegLiveness: true
+noVRegs:           true
+machineFunctionInfo:
+  wwmReservedRegs: ['$vgpr0_lo16']
+  isEntryFunction: false
+body:             |
+  bb.0:
+    liveins: $sgpr0, $sgpr1
+    ; GCN-LABEL: name: wwm_skip_shift_16bit_reg
+    ; GCN: liveins: $sgpr0, $sgpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: $sgpr2 = S_XOR_SAVEEXEC_B32 -1, implicit-def $exec, implicit-def dead $scc, implicit $exec
+    ; GCN-NEXT: SCRATCH_STORE_DWORD_SADDR killed $vgpr0_lo16, $sp_reg, 0, 0, implicit $exec, implicit $flat_scr :: (store (s16) into %stack.0, addrspace 5)
+    ; GCN-NEXT: $exec_lo = S_MOV_B32 killed $sgpr2
+    ; GCN-NEXT: renamable $vgpr0_hi16 = IMPLICIT_DEF
+    ; GCN-NEXT: $sgpr4 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
+    ; GCN-NEXT: $vgpr0_lo16 = IMPLICIT_DEF
+    ; GCN-NEXT: $vgpr0_lo16 = V_CNDMASK_B16_t16_e64 0, killed $vgpr0_hi16, 0, $vgpr0_lo16, $sgpr0, 0, implicit $exec
+    ; GCN-NEXT: $exec_lo = EXIT_STRICT_WWM killed renamable $sgpr4
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broxigarchen wrote:

I take a further check in this part.

The vulkan benchmark failure that this patch is trying to fix is caused by an entryFunction, and thus the wwm spill/restore are not happening. Update the test to just targetting the reg sorting fix in this patch.

For non entry-function case, it seems the CSR reg spill/restore is default using 32bit pseudo which need to be updated to support 16bit registers, and the spill/restore builder need to be changed as well. However, those requires more changes and I think it's better to do those in a seperate patch.

https://github.com/llvm/llvm-project/pull/135053