[llvm] 71329c6 - [AArch64][GlobalISel] Add test coverage for sub1.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 24 23:37:59 PDT 2025
Author: David Green
Date: 2025-04-25T07:37:55+01:00
New Revision: 71329c6da1cd467f23b63e4a2956420f45b2cee9
URL: https://github.com/llvm/llvm-project/commit/71329c6da1cd467f23b63e4a2956420f45b2cee9
DIFF: https://github.com/llvm/llvm-project/commit/71329c6da1cd467f23b63e4a2956420f45b2cee9.diff
LOG: [AArch64][GlobalISel] Add test coverage for sub1.ll. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/sub1.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sub1.ll b/llvm/test/CodeGen/AArch64/sub1.ll
index 01f8f312a8919..02893e2b63287 100644
--- a/llvm/test/CodeGen/AArch64/sub1.ll
+++ b/llvm/test/CodeGen/AArch64/sub1.ll
@@ -1,13 +1,22 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define i64 @sub1_disguised_constant(i64 %x) {
-; CHECK-LABEL: sub1_disguised_constant:
-; CHECK: // %bb.0:
-; CHECK-NEXT: sub w8, w0, #1
-; CHECK-NEXT: and w8, w0, w8
-; CHECK-NEXT: and x0, x8, #0xffff
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sub1_disguised_constant:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sub w8, w0, #1
+; CHECK-SD-NEXT: and w8, w0, w8
+; CHECK-SD-NEXT: and x0, x8, #0xffff
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sub1_disguised_constant:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
+; CHECK-GI-NEXT: and x9, x0, #0xffff
+; CHECK-GI-NEXT: add x8, x0, x8
+; CHECK-GI-NEXT: and x0, x9, x8
+; CHECK-GI-NEXT: ret
%a1 = and i64 %x, 65535
%a2 = add i64 %x, 65535
%r = and i64 %a1, %a2
@@ -15,12 +24,20 @@ define i64 @sub1_disguised_constant(i64 %x) {
}
define i8 @masked_sub_i8(i8 %x) {
-; CHECK-LABEL: masked_sub_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #5
-; CHECK-NEXT: and w8, w0, w8
-; CHECK-NEXT: eor w0, w8, #0x7
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: masked_sub_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #5 // =0x5
+; CHECK-SD-NEXT: and w8, w0, w8
+; CHECK-SD-NEXT: eor w0, w8, #0x7
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: masked_sub_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #5 // =0x5
+; CHECK-GI-NEXT: mov w9, #7 // =0x7
+; CHECK-GI-NEXT: and w8, w0, w8
+; CHECK-GI-NEXT: sub w0, w9, w8
+; CHECK-GI-NEXT: ret
%a = and i8 %x, 5
%m = sub i8 7, %a
ret i8 %m
@@ -29,12 +46,20 @@ define i8 @masked_sub_i8(i8 %x) {
; Borrow from the MSB is ok.
define i8 @masked_sub_high_bit_mask_i8(i8 %x) {
-; CHECK-LABEL: masked_sub_high_bit_mask_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #-96
-; CHECK-NEXT: and w8, w0, w8
-; CHECK-NEXT: eor w0, w8, #0x3c
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: masked_sub_high_bit_mask_i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #-96 // =0xffffffa0
+; CHECK-SD-NEXT: and w8, w0, w8
+; CHECK-SD-NEXT: eor w0, w8, #0x3c
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: masked_sub_high_bit_mask_i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #-96 // =0xffffffa0
+; CHECK-GI-NEXT: mov w9, #60 // =0x3c
+; CHECK-GI-NEXT: and w8, w0, w8
+; CHECK-GI-NEXT: sub w0, w9, w8
+; CHECK-GI-NEXT: ret
%maskx = and i8 %x, 160 ; 0b10100000
%s = sub i8 60, %maskx ; 0b00111100
ret i8 %s
@@ -43,7 +68,7 @@ define i8 @masked_sub_high_bit_mask_i8(i8 %x) {
define i8 @not_masked_sub_i8(i8 %x) {
; CHECK-LABEL: not_masked_sub_i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: mov w8, #7 // =0x7
; CHECK-NEXT: and w9, w0, #0x8
; CHECK-NEXT: sub w0, w8, w9
; CHECK-NEXT: ret
@@ -53,25 +78,41 @@ define i8 @not_masked_sub_i8(i8 %x) {
}
define i32 @masked_sub_i32(i32 %x) {
-; CHECK-LABEL: masked_sub_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #9
-; CHECK-NEXT: and w8, w0, w8
-; CHECK-NEXT: eor w0, w8, #0x1f
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: masked_sub_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #9 // =0x9
+; CHECK-SD-NEXT: and w8, w0, w8
+; CHECK-SD-NEXT: eor w0, w8, #0x1f
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: masked_sub_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov w8, #9 // =0x9
+; CHECK-GI-NEXT: mov w9, #31 // =0x1f
+; CHECK-GI-NEXT: and w8, w0, w8
+; CHECK-GI-NEXT: sub w0, w9, w8
+; CHECK-GI-NEXT: ret
%a = and i32 %x, 9
%m = sub i32 31, %a
ret i32 %m
}
define <4 x i32> @masked_sub_v4i32(<4 x i32> %x) {
-; CHECK-LABEL: masked_sub_v4i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: movi v1.4s, #42
-; CHECK-NEXT: movi v2.4s, #1, msl #8
-; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
-; CHECK-NEXT: eor v0.16b, v0.16b, v2.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: masked_sub_v4i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v1.4s, #42
+; CHECK-SD-NEXT: movi v2.4s, #1, msl #8
+; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-SD-NEXT: eor v0.16b, v0.16b, v2.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: masked_sub_v4i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi v1.4s, #42
+; CHECK-GI-NEXT: movi v2.4s, #1, msl #8
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: sub v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: ret
%a = and <4 x i32> %x, <i32 42, i32 42, i32 42, i32 42>
%m = sub <4 x i32> <i32 511, i32 511, i32 511, i32 511>, %a
ret <4 x i32> %m
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